JTAG boundary-scan helps your process in three ways: it saves your organization time, it is cost-effective and it strengthens the quality of your products. To explain how we do that, let’s look into some of the details.
The JTAG boundary-scan standard was developed to solve a fundamental, technical problem facing traditional PCB assembly test equipment, i.e. probing device pins in fine-pitch, high pin count SMD packages (in particular BGA’s). Embedding JTAG/boundary-scan logic in chips makes the pins readily accessible and allows test signals to be transmitted between devices, independent of the type of package or device complexity without external probing.
Testing is essential to guarantee the quality of your products. One possibility is to perform a functional test. However, functional testing has two main disadvantages: you don’t know if you covered all possible assembly defects, and íf you find a failure it is hard (time-consuming, costly) to diagnose its cause. These two shortcomings are addressed by structural testing.
But structural testing requires probing of device pins. With miniaturization, probing is no longer possible, and thus structural testing using external probes becomes impossible. With boundary-scan such external probing is no longer needed. Thus boundary-scan was developed in a way that in case of miniaturization structural testing is still possible.
In short: boundary-scan was developed to facilitate structural testing, also in case of miniaturization.
While the original standard focused on board testing, the JTAG interface was soon also used for in-system programming of devices (Flash memories, FPGAs, CPLDs, and microcontrollers). The JTAG boundary-scan standard now provides many advantages over traditional systems.
Traditional test equipment using probing techniques to access pins and signals on Printed Circuit Board Assemblies (PCBA’s) faces increasing challenges.
JTAG logic in chips
Examples of built-in resources in chips accessible through the JTAG interface are the boundary-scan register and the microcontroller debug logic.
The JTAG interface can not only be used for testing, but also to program devices on your PCBA’s.
JTAG BOUNDARY-SCAN, FIRMLY BASED ON IEEE STANDARDS
The serial interface and logic were originally developed by a group of test professionals from Philips, BT, GEC, TI and others known as JTAG (the Joint Test Action Group) throughout the late 1980s. The group continued as an IEEE working group to complete the final standard which then got the official name IEEE Std 1149.1, the IEEE Standard Test Access Port and Boundary-Scan Architecture. The standard was first released in 1990. Since then enhancements have been made and the latest update was done in 2013, see IEEE 1149.1-2013.
Happy to serve you!
We have been able to solve thousands of board test problems by actively engaging with our customers. Once you become a JTAG Technologies customer you are an integral part of our business with free access to our world-wide support network.