System DFT Guidelines

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System DFT Guidelines

Benefits of boundary-scan at system level

The benefits of implementing system level test access by extending boundary-scan to the backplane (creating a unified test strategy for board and system level based on the IEEE Std. 1149.1 architecture) can be enormous. We will just describe the possibilities and opportunities which you can translate these to your own situation.

The scope of this document is to present a number of Design-For-Test (DFT) guidelines that can be used for reference in support of implementing system level boundary-scan architecture within PCB designs. So that this architecture can utilised effectively in performing board level manufacturing structural testing and the in-system configuration of cPLD, FPGA’s and flash memory devices within a system level environment.

This document also describes how this architecture can be further utilised to provide an integrated dynamic test capability at both system level test and in a field diagnostic environment.