Assessing PCBA ‘testability’ and JTAG ‘accessibility’ from schematic data

An introduction to JTAG/Boundary-scan fault coverage analysisFeaturing:

* Free and low-cost tools for exposing accessibility

* Advanced tools for precise net-level analysis

* Presentation of fault coverage results

Fault coverage analysis is an important step in the design-for-test (DFT)process which is also an integral part of of the design teams workload. Early feedback of coverage issues at the schematic entry stage can avoid costly re-spins at later stages which lengthen time-to market which in turn can massively reduce profitability over a product’s life.

  • 10/03/2021
  • EU / CEST
  • 10:30 am

Happy to serve you!

We have been able to solve thousands of board test problems by actively engaging with our customers. Once you become a JTAG Technologies customer you are an integral part of our business with free access to our world-wide support network.