A new product design should be ready for production as soon as possible. The design should be well ‘testable’ to optimize the production yield. Design-for-test (DfT) guidelines and analysis tools assist the design engineer in creating testable designs without costing extra design time. During prototype debugging JTAG/boundary-scan tools help design engineers to focus on design problems and avoid losing valuable time on finding ‘trivial’ connectivity problems caused by poor soldering or other assembly errors.


When you see errors when bringing up a new design, hardware debug tools help you to determine if a design error, or a missing connection, like an unsoldered device pin, is causing the malfunctioning. JTAG Technologies debug tools use the boundary-scan capabilities of the JTAG devices in your design. Buzz and BuzzPlus let you observe the activity of signals and verify interactively the presence of a connection by ringing-out that connection. Use Clip/ActiveTest to drive and sense the inputs and outputs of non-JTAG devices connected with pins of a JTAG device. And let CoreCommander help you verify the connectivity between your microprocessor or microcontroller and memory and I/O devices at speed without the need for embedded software or firmware.


During product development you program FPGAs and CPLDs using the hardware and software provided by the design station for these devices. Flash memories and microcontrollers/DSPs (embedded flash) are programmed using the tools for developing and debugging embedded software. Our “In-system Device Programming Guide” provides valuable information to increase throughput and improve the convenience during the manufacturing process.


Often the JTAG controller that you have from your device vendor for programming the FPGAs or CPLDs can be used for debug purposes too since JTAG Technologies debug tools also support a number of JTAG controllers from FPGA vendors. Alternatively the single TAP JTAG Live controller or the 2 TAPs JT 3705/USB controller provide a good hardware solution to access the JTAG chains(s) on your board for hardware debugging and device programming. Optionally a JT 2111 DIOS module can be added to access connector pins via boundary-scan.


In production the boundary-scan capabilities can be used to test the PCBAs for manufacturing defects. By applying the Design-for-Test (DfT) rules from our “Board DfT Guidelines” the boundary-scan capabilities of your boards can be fully exploited resulting in the maximum achievable boundary-scan testability for your design. You can quickly assess the accessibility / testability of your design with JTAG Maps.
The JTAG capabilities can also be valuable at system level as is explained in our “System DfT Guidelines”. System level designs and devices are supported in our tools as well.


When you need to test a small batch of boards you can save yourself time with AutoBuzz. After learning the connectivity map from a known-good board or your board’s netlist, this tool can ring-out the boundary-scan connections of your board automatically and reveal failing devices and connections.
Further time savings result if you combine the AutoBuzz test with other tests for your board in a single Script application. In Studio also programming of the FPGAs on your boards can be added to this Script with a JAM, STAPL or SVF player that use the programming files generated by your FPGA development tools.

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