Composing a Production Sequence – AEX Manager Focus (английский)

Setting up a test/programming sequence using ProVision’s AEX Manager An overview of this comprehensive tool that is included in all ProVision Platform and generation suites

Includes sections on

* Simple sequencing
* Using the conditional branch controls
* Handling JFT applications using exit codes
* Launching external programs within a sequence

This webinar aims to inform test and development engineers how set-up an effective test & ISP sequence and store the results for future analysis.

Introduction to boundary-scan (английский)

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An eye-opener in the world of structural testing using JTAG/boundary-scan aka IEEE Std 1149.1. Many electronics assemblies already include JTAG/boundary-scan test circuitry which is either underused or not used at all.

This webinar aims to inform test and development engineers of the possibilities of this built-in test and device programming feature.

Includes sections on:

*Device-level technology * EXTEST and other instructions * Board-level test and programming possibilities * Options for test generation * Hardware controller options

More about boundary-scan – advanced topics (английский)

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Follow-up session to ‘An introduction to boundary-scan’. Featuring:

* Options for JTAG application development (ATPG vs Scripting)
* Testing using JTAG emulation modes
* Fault coverage assessment process
* Production implementation

Emulative Testing via the JTAG interface (английский)

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TAG testing is synonymous with boundary-scan (IEEE Std 1149.1). However not all devices with a JTAG port support boundary-scan and some that do have restricted access to some signal pins, and what about access to analog functions such as built- in ADC and DAC in today’s micros?

This webinar discusses how JTAG Technologies CoreCommander functions can be used to exploit the micro’s core (e.g. ARM, TriCore, MIPs…) power for board-level testing and more..

JTAG Functional Test (английский)

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How to use scripting systems such as Python to generate powerful  test programs to combat your boards (PCBAs)
potential assembly problems.

– Background and comparison with ‘traditional’ JTAG Testing.
– Available APIs
– JFT coded Examples

This webinar covers how effective boundary-scan board (PCBA) tests can be generated with simple tools and familiar languages.

Programming Devices via the JTAG Interface (английский)

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An insight into device ‘in-system’ programming JTAG/boundary-scan, or IEEE Std 1149.1.

Many electronics assemblies already include JTAG/boundary-scan circuitry for board test, but did you know this is often used for production configuration or field updates of your design..?

Includes sections on:

– Direct vs Indirect Programming
– Flash device programming
– PLDs and Micros

This webinar aims to inform test and development engineers how JTAG/boundary-scan is used to program devices already populated onto PCB assemblies.

Assessing PCBA ‘testability’ and JTAG ‘accessibility’ from schematic data (английский)

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An introduction to JTAG/Boundary-scan fault coverage analysisFeaturing:

* Free and low-cost tools for exposing accessibility

* Advanced tools for precise net-level analysis

* Presentation of fault coverage results

Fault coverage analysis is an important step in the design-for-test (DFT)process which is also an integral part of of the design teams workload. Early feedback of coverage issues at the schematic entry stage can avoid costly re-spins at later stages which lengthen time-to market which in turn can massively reduce profitability over a product’s life.

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