JTAG Testing (and more) using Core Emulation

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TAG testing is synonymous with boundary-scan (IEEE Std 1149.1). However not all devices with a JTAG port support boundary-scan and some that do have restricted access to some signal pins, and what about access to analog functions such as built- in ADC and DAC in today’s micros?

This webinar discusses how JTAG Technologies CoreCommander functions can be used to exploit the micro’s core (e.g. ARM, TriCore, MIPs…) power for board-level testing and more..


More about boundary-scan – advanced topics

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Follow-up session to ‘An introduction to boundary-scan’. Featuring:

* Options for JTAG application development (ATPG vs Scripting)
* Testing using JTAG emulation modes
* Fault coverage assessment process
* Production implementation


Introduction to boundary-scan

This live webinar has taken place, click watch, to view the recording of this webinar

An eye-opener in the world of structural testing using JTAG/boundary-scan aka IEEE Std 1149.1. Many electronics assemblies already include JTAG/boundary-scan test circuitry which is either underused or not used at all.

This webinar aims to inform test and development engineers of the possibilities of this built-in test and device programming feature.

Includes sections on:

*Device-level technology * EXTEST and other instructions * Board-level test and programming possibilities * Options for test generation * Hardware controller options

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