JTAG Live CoreCommander
CoreCommander routines take control of key processor core (e.g. ARM, PPC, X-scale, Cortex etc.) functions using the built-in emulation/debug functions found in today’s RISC and DSP cores. They have been developed to speed-up board testing and debug by enabling kernel-centric testing.
CoreCommander offer two modes of operation:
- Interactive – offering direct control of the core or;
- Python embedded – where controls can be scripted into a complete program.
JTAG Live Buzz is automatically included for free with this product.
- Overcomes deficiencies in boundary-scan registers
- Works with devices not compliant to IEEE std 1149.x
- Most popular processor cores supported (ARM PPC etc.)
- Code compatible with Python for test scripting
- Low-cost compared to other solutions.
- Supported by JTAG Technologies, JTAG Live and FTDI based controllers/interfaces
- Simple to use interactive GUI to perform core writes/reads
- Functions include ‘EnterDebug’, ‘ExitDebug’, ‘LoadMemory’, ‘SaveMemory’, ‘WritePC’, ‘ReadPC’
- Compatible with Python open-source scripting language.
- Works in tandem with JTAG Live Script – boundary-scan routines.
CoreCommander routines can be used to boost test coverage in applications that have only a small amount or even no IEEE std 1149.1 (conventional boundary-scan) test access options. By taking hold directly of the target processor’s core the user can write to or read from configuration registers and internal or external memory spaces.
Micro Cores currently supported are: AD BlackFin, ARM 7/9/11/Cortex M/Cortex A/R, Freescale PPC, Infineon TriCore, X-scale PXA27x/27x/3xx, TI C2000, Microchip PIC32 /DSPIC, NXP ColdFire & ST C166
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