JTAG Live CoreCommander
CoreCommander routines take control of key processor core (e.g. ARM, PPC, X-scale, Cortex etc.) functions using the built-in emulation/debug functions found in today’s RISC and DSP cores. They have been developed to speed-up board testing and debug by enabling kernel-centric testing.
CoreCommander offer two modes of operation:
- Interactive – offering direct control of the core or;
- Python embedded – where controls can be scripted into a complete program.
JTAG Live Buzz is automatically included for free with this product.
- Overcomes deficiencies in boundary-scan registers
- Works with devices not compliant to IEEE std 1149.x
- Most popular processor cores supported (ARM PPC etc.)
- Code compatible with Python for test scripting
- Low-cost compared to other solutions.
- Supported by JTAG Technologies, JTAG Live and FTDI based controllers/interfaces
- Simple to use interactive GUI to perform core writes/reads
- Functions include ‘EnterDebug’, ‘ExitDebug’, ‘LoadMemory’, ‘SaveMemory’, ‘WritePC’, ‘ReadPC’
- Compatible with Python open-source scripting language.
- Works in tandem with JTAG Live Script – boundary-scan routines.
CoreCommander routines can be used to boost test coverage in applications that have only a small amount or even no IEEE std 1149.1 (conventional boundary-scan) test access options. By taking hold directly of the target processor’s core the user can write to or read from configuration registers and internal or external memory spaces.
|Analog Devices||Blackfin BF5xx|
|ARM – Cortex-A/R (For A5,A7,A8,A9,A15,R4,R5,R7)|
|ARM – Cortex-M (For M0,M1,M3,M4,M7, M0-SWD,M1-SWD,M3-SWD,M4-SWD,M7-SWD)|
|Intel (Altera)||JTAG Technologies Translator for FPGAs|
|Marvell||XSCALE – PXA25x / PXA26x|
|XSCALE – PXA3xx|
|XSCALE – PXA27x / IXP4xx|
|MPC5xx / MPC8xx|
|Renesas||RH850/D1x / RH850/f1x|
|Texas Instruments||C28x (TMS320 C2000 series)|
|Xilinx||JTAG Technologies Translator for FPGAs|
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