Building high speed memory cluster and connectivity tests with CTPG_M and a supporting CoreCommander module that allows communication with your device’s internal IP is all that is needed to build high-speed memory and connectivity cluster tests in ProVision.
Led by an increasing desire to test DDRx and other memory types at true system speed JTAG Technologies has developed the new CoreCommander Test Program Generator (CTPG_M) for ProVision. CTPG_M overcomes many of the issues associated with testing of memory clusters using conventional boundary-scan (IEEE Std 1149.1) techniques, including the lack of a boundary-scan register (generally in smaller CPUs), insufficient access to all memory signals (most notably synchronous memory clocks) and also the inability to test using write/read cycles running at full system speed. By using the power of the embedded emulation/debug logic and the embedded memory controller, tests can be developed automatically to overcome the issues listed above, allowing faster and more effective testing. The system utilises existing debug/emulation support options built-into microprocessors or downloaded into FPGAs (see CoreCommander). CTPG_M is available now as an option to JTAG ProVision software (CD 23 and above). It is fully compatible with all JTAG Technologies tester hardware and diagnostics system allowing pin-level diagnostic reports to be produced for test engineers, production technicians and others. Test results can thus also be viewed in layout or schematic views provided by JTAG Technologies Visualizer tools.
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