CoreCommander

While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote ‘kernel-centric’ testing. Similarly, in the case of today’s Field Programmable Gate Arrays (FPGAs) test engineers can ‘bridge’ from the JTAG interface to the resources of the gate array itself. Our CoreCommander FPGA product implements a ‘translator’ interface that allows our JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone, CoreConnect, AXI, Avalon etc.).

Features

  • JTAG control of 'processors, and FPGAs via core debug access or embedded logic
  • Most popular cores & FPGAs supported
  • Create 'at-speed' cluster tests and flash applications
  • Overcomes deficiencies in boundary-scan registers
  • Works with devices not compliant to IEEE Std. 1149.x
  • Most popular processor cores & FPGAs supported (ARM PPC etc.)
  • Code compatible with Python for test scripting
  • Low-cost compared to other solutions.

CoreCommander Micro routines can be used to boost test coverage in applications that have only a small amount or even no IEEE std 1149.1 (conventional boundary-scan) test access options. By taking hold directly of the target processor’s core the user can write to or read from configuration registers and internal or external memory spaces. CoreCommander FPGA works by leveraging existing IP that might form part of the configured function of the device. Elements such as DDR memory controllers can now be ‘commanded’ via JTAG access through a translator block and bus systems like Avalon and Wishbone.

  • Supported by JTAG Technologies, JTAG Live and FTDI based controllers/interfaces
  • Simple to use interactive GUI to perform core writes/reads
  • Processor functions include ‘EnterDebug’, ‘ExitDebug’, ‘LoadMemory’, ‘SaveMemory’, ‘WritePC’, ‘ReadPC’
  • FPGA users benefit from IP access via standard busses Avalon, AMBA, CoreConnect and Wishbone
  • Micro Cores supported are: ARM 7/9/11/Cortex M, Freescale PPC, X-scale PXA27x/27x/3xx, TI C2000, Microchip PIC32 & ST C166
  • Works in tandem with JFT- Python JTAG/boundary-scan routines.

Microprocessor/microcontroller devices featureing the following MPU cores are supported:-

ARM – ARM7, ARM9, ARM11, Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A15, Cortex-M0, Cortex-M0 SWD, Cortex-M1, Cortex-M1 SWD, Cortex-M3, Cortex-M3 SWD, Cortex-M4, Cortex-M4 SWD, Cortex-R4, Cortex-R5, Cortex-R7

Altera – ALTERA FPGA

Analog Devices – Blackfin

Freescale/NXP/Qualcomm – ColdFire, PowerPC, MPC5xx, MPC5xxx, MPC8xx

Infineon – Tricore, C166

Marvell – X-scale PXA25x/27x/3xx,

Microchip – PIC32

Texas Instruments – C2000

XSCALE – IXP4xx, PXA3xx, PXA25x, PXA26x, PXA27x

Xilinx – Artix7, Kintex7, Spartan3, Spartan6, Virtex, Virtex2, Virtex4, Virtex5, Virtex6, Virtex7, Virtex-E, Zynq

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