CoreCommander
CoreCommander can be used as interactive jtag hardware debug tool via its high-level GUI. In this jtag interface register access commands or full memory reads and writes can be selected and executed with a direct view of the results. Sequences of commands can be re-played within the interactive window or exported into a Python editor. The interactive usage is particularly valuable during hardware bring up and debugging in design and (field) service
While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote ‘kernel-centric’ testing. Similarly, in the case of today’s Field Programmable Gate Arrays (FPGAs) test engineers can ‘bridge’ from the JTAG interface to the resources of the gate array itself. Our CoreCommander FPGA product implements a ‘translator’ interface that allows our JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone, CoreConnect, AXI, Avalon etc.).
CoreCommander is also available through our webshop.
Features
- JTAG control of 'processors, and FPGAs via core debug access or embedded logic
- Most popular cores & FPGAs supported
- Create 'at-speed' cluster tests and flash applications
- Overcomes deficiencies in boundary-scan registers
- Works with devices not compliant to IEEE Std. 1149.x
- Most popular processor cores & FPGAs supported (ARM PPC etc.)
- Code compatible with Python for test scripting
- Low-cost compared to other solutions.
CoreCommander Micro routines can be used to boost test coverage in applications that have only a small amount or even no IEEE std 1149.1 (conventional boundary-scan) test access options. By taking hold directly of the target processor’s core the user can write to or read from configuration registers and internal or external memory spaces. CoreCommander FPGA works by leveraging existing IP that might form part of the configured function of the device. Elements such as DDR memory controllers can now be ‘commanded’ via JTAG access through a translator block and bus systems like Avalon and Wishbone.
- Supported by JTAG Technologies, JTAG Live and FTDI based controllers/interfaces
- Simple to use interactive GUI to perform core writes/reads
- Processor functions include ‘EnterDebug’, ‘ExitDebug’, ‘LoadMemory’, ‘SaveMemory’, ‘WritePC’, ‘ReadPC’
- FPGA users benefit from IP access via standard busses Avalon, AMBA, CoreConnect and Wishbone
- Micro Cores supported are: ARM 7/9/11/Cortex M, Freescale PPC, X-scale PXA27x/27x/3xx, TI C2000, Microchip PIC32 & ST C166
- Works in tandem with JFT- Python JTAG/boundary-scan routines.
| Vendor | xxx | Microprocessor (cores) |
|---|---|---|
| Analog Devices | Blackfin BF5xx | |
| Blackfin BF60x | ||
| ARM | ARM7 | |
| ARM9 | ||
| ARM11 | ||
| ARM – Cortex-A/R (For A5,A7,A8,A9,A15,R4,R5,R7) | ||
| ARM – Cortex-M (For M0,M1,M3,M4,M7, M0-SWD,M1-SWD,M3-SWD,M4-SWD,M7-SWD) | ||
| Infineon | C166 | |
| Tricore | ||
| Intel (Altera) | JTAG Technologies Translator for FPGAs | |
| Marvell | XSCALE – PXA25x / PXA26x | |
| XSCALE – PXA3xx | ||
| XSCALE – PXA27x / IXP4xx | ||
| Microchip | PIC32 | |
| NXP (Freescale) | Coldfire | |
| MPC5xx / MPC8xx | ||
| MPC5xxx | ||
| Renesas | RH850/D1x / RH850/f1x | |
| STMicroelectronics | SPC5 | |
| Texas Instruments | C28x (TMS320 C2000 series) | |
| Xilinx | JTAG Technologies Translator for FPGAs |
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