The implementation of Design-for-Manufacturing (DfM) alongside the use of high quality assembly and inspection equipment minimizes the chance for assembly errors. In spite of this, however, assembly errors do occur and PCBAs must be tested to detect these errors in an effort to achieve PCBAs with zero defects.
A test sequence (also known as TestPlan) is used to execute individual actions (step types) such as power switching, structural or functional tests, limit compares or device programming actions in a logical order.
Various parameters determine the type of test and programming hardware that fits best. Such parameters include performance, form factor, integration possibilities with other test stations already in use, etc.
In production, when devices are programmed as part of the board configuration process, a complete range of different devices and device types must be supported. For efficiency reasons such programming should ideally be undertaken using the same hardware as used for testing
The JTAG Live Controller is USB connected and powered and features a single test access port in JTAG Technologies standard 10-way IDC pin-out. The JTAG Live controller is a smart, low-cost and easy-to-use USB JTAG/Boundary-scan interface.
It offers a maximum programmable TCK speed of 6 MHz and also features programmable output voltages and input thresholds.
The JT 3705/USB Explorer is a low-cost two port USB powered boundary-scan controller interface specifically suited for low volume testing and in-system programming of (C)PLDs. Explorer supports two fully-compliant boundary-scan test access ports (TAPs) which can be synchronized for test purposes.
Features include 6MHz maximum TCK frequency and adjustable input and output thresholds.
The JT 3705/USB is support by ProVison‘s custom combined instrument feature that allows multiple controllers to act as one.
The JT 5705 series offer a unique combination of JTAG TAP controller (tester) interfaces plus digital and analog I/O in compact desktop package.
Use the ‘mixed-signal’ features to measure power supplies, clock frequencies or test DACs and ADCs. Add your own capability through use of CoreCommander FPGA our generic bridge/translator system.
The JT 5705/USB version (pictured right) is a desktop model with 2 TAPs and 64 I/O making it ideal for hardware validation or small-scale production test. Maximum TCK speed is 15 MHz and all voltages are fully programmable. The JT5705/FXT is the ‘fixture’ version supplied as a pcb assembly only with optional ‘break-out’ boards available depending on your application.
In co-operation with Takaya’s principal European agents, Itochu, JTAG Technologies have developed an integration solution that utilises four I/O signals from the standard JT 37×7 controller JT2147 QuadPod connected to the four flying probes of a 9400 system. A custom version of JTAG’s execution software then interacts with the driving and sensing electronics used by the probes of the Takaya. Signals can be driven via boundary-scan and sensed with the flying probes or the other way around. Results and diagnostics are presented in the Takaya software environment.
Users wishing to integrate JTAG Technologies boundary-scan applications with Teradyne teststations and GR228x have two options. The first uses Teradyne’s own Deep Serial Memory (DSM) card as the boundary-scan interface/controller while the other solution is based on our standard JT 37×7 controller which may be combined with a dedicated version of our QuadPod called the JT 2147/CFM. The DSM based solution allows you to mix stimulus and response via ICT pins/nails with boundary-scan driving and sensing capabilities to access nodes on your target. The JT 37×7 based solution is more suited to applications requiring fast Flash or PLD programming via boundary-scan access. Both solutions are controlled by the Teradyne GUI and reports with full pin level diagnostics are fed back into the Teradyne report generator.
Our ProVision development tools can be used to generate the boundary-scan based test patterns which are provided to the Teradyne test development tools for further processing.
Symphony AP is the result of teamwork between JTAG Technologies and the engineers from Huntron. The Symphony AP package is a combination of our standard QuadPod plus a JT 37×7/TSI controller, ProVision Platform and BSD diagnostics software. This package lets you combine probe access provided by Huntron’s roving prober and boundary-scan access in one test. ProVision also controls the placement of the probe.
Combining the analog signature analysis (I-V trace) capability of the Huntron system with boundary-scan creates an excellent mixed signal tester platform.
JTAG Technologies has a long-standing partnership with Seica Spa, Italy with whom we developed one of the earliest flying-probe and boundary-scan test integrations. JTAG Technologies Symphony Pilot system utilises standard JT 37×7 DataBlaster hardware to allow test and in-system programming applications to be executed and diagnosed on a full range of Seica test platforms.
Through our close working relationship with the engineers of DigitalTest GmbH in Germany, a dedicated version of our JT 3727 DataBlaster controller has been developed that fits perfectly into the DigitalTest MTS testers. This JT 3727/DPC boundary-scan controller connects the TAP signals via the tester’s fixture/interface directly to your target. In addition an enhanced version of our execution software has been developed that allows synchronised interaction with the pin cards of the MTS tester and its GUI software (CITE32). Digital signals can be driven via boundary-scan and sensed with the I/O pins of the MTS machine or the other way around. Results and diagnostics are presented in the CITE32 GUI.
During the validation of the developed test applications, JTAG ProVision can also control the MTS tester.
The integration of JTAG/Boundary-scan with 6TL’s brand of functional test equipment (FTE) provides a best of both solution that can address the majority of board and system test requirements. Since boundary-scan and functional test are complementary test methods, this combination often provides an optimal strategy with lowest overall cost and maximum coverage for anticipated fault types. Using the built-in JTAG controller capability of the YAV9JTAG card also reduces cost and resource overheads for basic applications
Test and in-system programming applications are generated on JTAG Technologies’ development tools (JTAG ProVision or Classic) and can be easily imported into the 6TL environment.
The Symphony 3070 product is a combination of dedicated hardware based on JTAG Technologies’ DataBlaster technology (JT 37×7/APC) and software that allows you to execute boundary-scan applications developed with our ProVision tools on your 3070 tester – both Unix and Windows operating systems are supported. Results and diagnostic reports are presented in the Keysight/Agilent GUI.
The bundled solution of our JT 37×7/APC controller, execution software and diagnostics software is sold via JTAG Technologies as Symphony 3070/APC-x7/PC or as Symphony 3070/APC-x7/Unix.
Together with the engineers of Viavi Solutions we developed an Viavi dedicated version of our QuadPod that fits perfectly in to a 42xx tester. This JT 2147/AGP connects the standard JT 37×7 controller (PCI or TSI) via your fixture to your target. In addition an enhanced version of our execution software has been developed that interacts with the pin cards of the Viavi and its GUI. Digital signals can be driven via boundary-scan and sensed with the I/O pins of the Viavi machine or the other way around. Results and diagnostics are presented in the Viavi environment.
The bundled solution of a JT 37×7, JT 2147/AGP, boundary-scan execution software, diagnostics and an MTL controller code layer is exclusively sold via Viavi. For more information visit the Viavi website.
Integration solutions for the current 5800 series are also available and are based around the PXI version of the DataBlaster JT 37×7/PXI
The JTAG Provision Boundary-scan Integrated Development Environment (IDE) is a test and programming software suite that is used in production and manufaturing to generate boundary-scan tests and in-system programming applications for assembled PCBs and systems. This integrated professional JTAG boundary-scan development environment (IDE) software tool is fully automated and supports the import of design data from over 30 different EDA and CAD/CAM systems. Other key data inputs are JTAG device BSDL (description) models and a large, well-maintained model library describing thousands of non-JTAG devices which includes memories, bus logic, and other active and passive parts.
How it works
With the ProVision boundary-scan software suite you can rapidly generate a wide range of test and programming applications using a project database built up from the inputs above. All applications can be optimized, validated and run within the ProVision environment prior to delivery of the finished test sequences to the manufacturing and/or testing facility. ProVision comes with a Built-in Boundary-scan test sequencer for production ready test plans
ProVision’s development features are tightly integrated with JTAG Technologies’ advanced test coverage analysis tool and with JTAG Visualizer graphical display system for design schematics and layouts. You can use these professional JTAG tooling to rapidly assess the thoroughness of the test during development and to make improvements prior to release.
The use of JTAG/Boundary-scan combined with a number of mixed signal IO channels brings a new dimension to the bench-top ATE market. The JT 5705/FXT is a highly compact (less than 10cm x10cm) multifunction USB-powered instrument in its own right and offers two full JTAG TAPs (Test Access Ports) and 64 IO channels with a combination of Digital, Analog and Frequency measurement capabilities. The matching JT 2702/xx range of carrier boards have been designed to allow seamless integration of this powerful capability into an array of popular bench fixtures.
The already impressive specification of the JT 5705/FXT is enhanced by the addition of multiplexing circuitry on the carriers to increases the effective channel count further.
Advanced users can also take advantage of the FPGA technology used by the JT 5705/FXT to create custom applications/instruments, controlled through JTAG’s unique CoreCommander FPGA software.
SCIL (Scan Configured Interface Logic) modules are a range of hardware functions usually pre-programmed into pods that take the place of a regular TAP pod within the JT 37×7 DataBlaster’s QuadPod system. Alternative ‘hosts’ for SCIL functions can also be the JT 2111/MPV (desktop DIOS) or the JT 5112 (MIOS). Currently available SCIL modules for enhancing test coverage are counter/timer and pattern generator/comparator units. Other SCIL modules are used in tandem with a SCIP (Serial Controlled In-system Programming) software options for in-system programming purposes. SCIP/SCIL combinations are used for programming Freescale parts via BDM, and Mono8 interfaces. SPI, I2C, SWD, and Microchip custom one-wire protocols are also supported.
Further SCIL module functions can be developed upon request, simply contact us or your local sales office.
JTAG Technologies BSDL generation/verification system combines advanced software with a unique hardware interface and automatically verifies an existing BSDL (Boundary-Scan Description Language) file or creates a BSDL file for the device if none exists from a known good sample device. The system complies with the recognized standard for BSDL descriptions – IEEE Std. 1149.1b . BSDL files describe the boundary-scan characteristics of a specific device in terms of scan register lengths, ID codes, instruction codes, etc.. and are a fundamental input to ATPG (e.g. ProVision) and other boundary-scan software tools.
JTAG TapCommunicator facilitates remote execution and diagnostics of boundary-scan applications, regardless of distance or environmental difficulties. The off-the-shelf system is based on a one gigabit ethernet connection (IEEE Std 802.3z) providing virtually unlimited range between the controller and target. TapCommunicator is based on the ‘licencable’ TapSpacer IP, technology that allows any (packetised) communication link to be used. For solutions using communication links other than Ethernet, contact JTAG Technologies.
The standard TapCommunicator system consists of an “uplink” or primary module (JT 2143), located in proximity to the boundary-scan controller, and one or more “downlink” or secondary (JT 2144) modules at the target. Licenced TapSpacer systems will work in a similar way though it is expected the compact logic code (for uplink and downlink) will be integrated into the users own ASIC or FPGA.
The JT 5112 MIOS JTAG/Boundary-scan mixed signal I/O with analog output module , simply add mixed-signal stimulus and measurement capabilities to your current JTAG test system.
Available in an impact-resistant enclosure or as a fixture-embedded version (/FXT) the JT 5112 works with all JT 37xx series of controllers. Measure and source analog values up to 30V on up to eight channels. Digital I/O on up to 64 channels. Also features frequency measurement capability and user programmable functions. Connections are via standard 0.1″ IDC plugs on the front of the unit. JTAG TAP and power connections at the rear.
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The JT 2149/DAF is a compact, mixed-signal (Digital/Analog/Frequency) measurement module for use in JTAG Technologies’ widely-used JT 2147 (QuadPod) signal conditioning interface. The DAF module has been designed to replace a regular TAP Pod and provides 28 measurement channels plus a clock generator. When connected to a circuit board via edge connector or test fixture/jig test pins, the module enhances standard digital boundary-scan tests by enabling a series of analog and frequency measurements to be made.
The new-concept, industrial JTAG-powered PCB tester-programmer the JT 57xx/RMIc ‘CombiSystem’ comprises a sleek base-level 19″ rack-mount chassis assembly that can house up to four customer-specified modules chosen from various JTAG (IEEE 1149.x) controllers, digital IO and analog IO and other measurement modules.
The modules are either ½ rack or ¼ rack width and are available as follows:
JT 5705/RMIc module (¼ width)
- 2 TAPs (15MHz)
- 64 mixed signal IO (MIOS) channels
JT 37×7/RMIc module (½ width)
- 4 TAPs(40MHz)
- 16 static IO channels
- optionally 64 DIOS channels (DIO-64 version only)
JT 5112/RMIc module (¼ width)
- 64 mixed signal IO (MIOS) channels
JT 5111/RMIc module (¼ width)
- 64 digital IO (DIOS) channels
Each of the modules offer similar specifications to their bench-top equivalents but benefit from higher channel and TAP density, smaller footprint and lower overall cost. By mixing and matching the modules users can configure almost any type of JTAG/boundary-scan tester-programmer that might be needed to build the most cost-effective solution.
The JT 2147 QuadPOD high speed device programmer and flash programmer comprises JT 2148 transceiver and four independent, programmable JT 2149 TAP PODs and provides signal conditioning for the DataBlaster series of boundary-scan controllers. Used for gang, parallel, fast testing / Programming of devices.
TAP pods can be housed integrally within the transceiver or they can be detached and reconnected via the (optional) one meter extension cable. The JT 2148 transceiver is available in standard (/10) or industrial (/13) variants. The /13 variant includes a SCSI cable splitter to allow system integrators to use flat ribbon cables into the transceiver itself which often simplifies fixture building.
A fixture-embedded variant of the JT 2147 is available as part reference JT 2147/FXT. This unit integrates the function of the transceiver and four pod onto a single assembly. This variant can also support 64 DIOS channels and SCIL functions (see more images below for a picture of the JT 2147/FXT).
The JT 2111/MPV is a 64 channel boundary-scan digital I/O scan module enclosed in an impact resistant housing. The module is designed to test and control edge connectors, on-board connectors and logic clusters in boundary-scan applications. Multiple modules can be connected serially to increase the number of I/Os. Available with 96-pin DIN 41612 connectors and 20-pin 0.1″ pitch IDC connectors.
This JT2111/MPV DIOS module is also available through our webshop.
The JT37x7 DataBlasters are a family of high speed and performance, up to 40 MHz TCK, boundary-scan controllers available in bench-top (USB/E-net/FireWire), PXI(e)and PCI(e) formats.
The controllers are targeted at demanding manufacturing test applications, fast in-system flash memory programming and programmable logic configuration. The JT 37×7 is available in different operating levels (memory options) to suit your specific environment and application. Each unit is supplied with a four TAP port signal conditioning module the JT 2147 ‘QuadPOD‘
See the form factors, more images and applications tabs below for more details.
The JT 2137 pod remains a popular choice for DataBlaster controller installations that require a compact signal conditioning pod embedded within a test fixture. The JT 2137 features four test access ports which together may be set for 5v or 3.3V TTL thresholds, although additional plug-in adapters are available that allow alternative thresholds to be set on a TAP by TAP basis (contact your local sales office for details). The 20-way 0.1″ IDC TAP headers comply with the standard JTAG Technologies 20-way pin-out and provide the additional flash programming controls Read/Busy and AutoWrite.
The JT 2147/eDAK is a new variant of the JTAG Technologies QuadPOD signal conditioning interface specifically designed for use within a MAC Panel ‘Scout’ mass interconnect interface. The unit integrates both the JT 2148 transceiver circuitry plus four independent, programmable TAP modules (two of type JT 2149 and two of type JT2149/MPV) on a single board that matches the MAC Panel Direct Access Kit (DAK) form factor. Overall this configuration offers four Test Access Ports, 64 Digital IO Scan channels and reconfigurable (SCIL) capabilities
The JT 2147/VPC is a variant of the JTAG Technologies QuadPOD signal conditioning interface specifically designed for use within Virginia Panel Corporation’s mass interconnect interface. The unit integrates both the JT 2148 transceiver circuitry, two independent, programmable TAP modules (of type JT 2149) and two TAP modules with I/O (of type JT 2149/MPV) on a single board that interfaces via the VPC QuadraPaddle connectors type G20x or G14x.
The JT 2122/MPV DIOS (digital I/O scan module) increases the coverage and improves the diagnostic resolution of boundary-scan testing by extending test access to connectors and/or test points. JT 2122/MPV DIOS provides bi-directional parallel-scan access to up to 128 or 133 I/Os in a standard DIMM-168 module.
The TAP signals can be accessed via the ‘fingers’ of the 168 pin module connector or a separate 10-pin connector. A TAP-out can be used to daisy-chain to another DIOS module or to a scan chain on the target board.
The JT 2128 DIOS module increases fault coverage and improves the diagnostic resolution. The JT 2128 provides bi-directional parallel-scan access to up to 133 I/O channels grouped in three segments, each of which can be individually bypassed. The JT 2128 is designed for easy insertion in standard 168-pin DIMM sockets either on a target board, JT 2702/DDC break-out module or in a test fixture.
The JT 2127 Socket Test Module (STM) family has been designed for manufacturing test of PCB DIMM sockets. They offer easy insertion in standard DIMM sockets on a target board and will test all active signals as well as the analog voltages on the individual power pins (such as Vdd, Vddq, Vref and Vddspd). JT 2127 STMs provide a complete structural test of the DIMM sockets.
See also specifications section below.
JT 2702/PCI-Slot is a fixturing solution for the production testing of 32-bit and 64-bit PCI plug-in cards. The JT 2702/PCI-Slot features sacrificial female sockets compatible with both 32-bit and 64-bit versions of the PCI bus. On the reverse side of the test adapter board, two sockets house regular JT 2122/MPV DIMM DIOS modules that provide the DIOS channels required to test the PCI bus signals.
During 32-bit bus testing 19 ‘spare’ I/O channels are available at an IDC header that can be used for fault detection on other UUT connectors or test points. During 64-bit bus testing a total of 83 spare channels are available.
The JT 2127/Flex STM memory socket tester is a family of hardware adapters specifically designed for the testing of of PCB-mounted DIMM & SODIMM sockets using a JTAG/boundary-scan controller and supporting software. The testing of memory sockets has always been troublesome for test and production engineers using JTAG/boundary-scan systems. Even when it is possible to create memory writes/reads from a boundary-scan compliant access device on the UUT (Unit Under Test), the initialisation process may fail leaving you with little diagnostics information. What’s more it can still be uncertain whether fault lays with the DIMM module itself or the socket. Using the new JT 2127-Flex system from JTAG Technologies you get pin-point diagnostics from a known-good test interface so you can be certain that your socket is soldered correctly.
The JT 2135 allows TAP signals to be extended away from the base JT 2137 (classic pod) by up to 1 meter and retain full pod’s frequency specifications. The active circuitry inside the JT 2135 compensates for the TDO signal return time of the longer interface cable. Multiple JT 2135s can be implemented if a longer extension is required.
The JT 2139 is a TAP signal isolation module designed for use in combinational test systems that utilise multiple instrument interfaces. To avoid parasitic capacitance effects and/or unwanted ground loops the JT 2139 can be used to completely galvanically isolate any JTAG Technologies boundary-scan controller from the remainder of the instrumentation system. JT 2139 isolators are a standard component of the JTAG Technologies ‘Symphony’ systems that integrate boundary-scan with In-Circuits Testers etc..
JT 2149-CON is the safe way to connect TAP pods and SCIL modules to the JT 37×7/RMI – 19″ rack-mount controller with DIOS.
Included in the package is the connector/blanking plate that allows an easy connection to a JT 2149/RMI (the TAP pod for the RMI) via the supplied 1 metre extender cable.
The JT 2154 is an experiment board based on National Semiconductor’s STA111 device, aimed at users looking to utilise addressable bridge/multiplexors within their designs, and thus set-up ‘system level’ JTAG access. The unit can also be used in semi-permanent installations to expand the TAP (Test Access Port) count on JTAG Technologies controllers in order to address highly segmented designs. Built-in support for ScanBridge-type devices within ProVision allows easy set-up of TAP assignments and device addressing.
The JT 2156 training board has been devised to demonstrate all the latest features and test techniques available to users of JTAG Technologies’ ProVision & JTAG Live application development systems. As well as a modern ARM Core processor, the design also includes an Altera Cyclone FPGA, DDR Memory, Ethernet PHY, and several SPI and I2C peripheral parts. The JT2156 is shipped with a comprehensive self-study manual for getting to know the in-depth features of ProVision and/or JTAGLive Studio. For Altium users the design also serves as an example of how to adapt the Nano board into a realistic custom design.
The PMBus is simply a protocol that defines communication between power conversion devices, using SMBus (System Management Bus) as the physical layer. SMBus is in turn based on I2C with additional fault tolerant and error correction features.
In a standard PMBus set-up a separate interface header or a dedicated master devices must be employed to communicate with PMBus slaves. Using PMBusProg however allows the user to harness the power of the existing JTAG/boundary-scan driver/sensor pins and use these to synthesise a PMBus master.
JTAG Functional Test system (JFT) is a simple to use DLL Application Program Interface (API) with a series of software modules that support boundary-scan test and programming activities under Python, National Instruments’ LabVIEW and Microsoft .NET framework. Using JFT users can create JTAG/boundary-scan test application scripts, LabVIEW VIs or programs for PCB assemblies and systems that control individual driver/sensor pins, groups of pins declared as variables or register bits.
These applications are typically used to test logic devices or mixed signal clusters and can also be transformed into re-usable test ‘modules’. Pairing JFT with JTAG CoreCommander emulative test modules gives an effective, low-cost system for performing tests through embedded device peripherals (ADCs, Memory Controllers etc..)
JTAG Visualizer is an advanced graphical and layout viewer and data management system for PCB schematics and layouts. Visualizer integrates seamlessly with the JTAG Technologies family of boundary-scan products such as the ProVision application development platform. It accepts PCB data from a variety of CAD, CAM and EDA tools. In design, Visualizer provides DfT (design for test) feedback to the user by enabling a graphical view of fault coverage on their design. In manufacture and test, Visualizer can be used to highlight faulty nets (short circuits, opens, stuck-ats etc.) in both layout and schematics views. Visualizer also supports cross-probing between schematics and layout as well as a layout underside ‘flip’ view mode.
JTAG Technologies’ ‘Classic’ Production Stand-Alone package (PSA) has, for many years, been the standard execution system operated in CEM and OEM factories when an independent boundary-scan test and/or device programming station is required. Introduced in the late 1990s to support applications generated by our ‘Classic’ development tools, several thousand PSA systems are still in use today. For new projects however ProVision Platform run-time system is usually recommended
Using PSA, test engineers can build sequences of applications in the built-in AEX (Application EXecutive) manager using if, then, else, and goto capabilities. Sequence builders can also include additional capabilities through DOS/Win command line calls, create serial number logged test reports, export tests results to a database etc.. PSA includes drivers for all JTAG Technologies controller hardware past and present.
With JTAG ProVision Flash you can program thousands of different flash types – even NAND and serial devices – using a variety of supported data formats. Flash memory programming applications include erase, blank-check, program, verify, lock, unlock, and read_id, which can be created automatically for over 20,000 parts. Generally flash in-system programming (ISP) applications utilise the built-in boundary-scan register of IEEE 1149.1 parts to control write/read cycles, however where programmable logic iterface directly with flash, bespoke IP applications can be used to greatly increase data throughput.
JTAG ProVision Flash is the easiest, fastest tool suite for development of ISP (In-System Programming) applications. It offers unmatched flexibility – multiple chains, multiboard designs and a re-usable project database.
Almost all today’s programmable logic devices (CPLDs and FPGAs) now utilise the IEEE std 1149.1 interface port to access their proprietary configuration circuits. Until 2001 the popular SVF (Serial Vector Format) was considered the de facto standard for streaming data into these parts and SVF remains popular to this day.
However as the IC vendors vied to produce the optimum data format/language for programming devices ‘in-system’ other standards appeared (JAM, STAPL, XSVF etc..) until the IEEE standards committee approved a universal standard that could be applied across designs bearing multiple vendor devices. The IEEE Std 1532 was finally approved in 2001 and as part of that standard a universal data format ‘ISC’ was introduced alongside enhanced BSDL models for compliant programmable parts.
Since the very first PLDs with JTAG programming were introduced JTAG Technologies have developed timely support packages that allow manufacturers to program all vendor parts at high speed. Today that support is provided through JTAG ProVision and the PIP and Symphony tester integration packages.
JTAG Technologies offers a range of options that can be used by engineers to improve their device programming facilities without adding much in the way of additional hardware. Our solutions for programming embedded (flash) memories of Microprocessors and DSPs are also known as SCIP (Serial Controlled IC Programmer) modules. The family comprises a wide range of software modules that can be used by test and production engineers to broaden the scope of their in-system device programming facilities without adding much or anything in the way of additional interface hardware.
While many devices have standardised on JTAG (IEEE Std 1149.1) as hardware interface for programming and testing there has been little in the way of standardisation regarding the way internal (flash) memories are programmed. The use of ‘Private’ instructions and non-standard state machine implementations have meant that some JTAG/boundary-scan tool-sets are unable to cope with the variety of devices that now use JTAG as their programming interface. Furthermore there exists a secondary layer of devices that use other, often lower pin count, interfaces to support their programming. Examples of these alternative interfaces are BDM, SPI, SWD (ARM Single Wire Debug) etc.. JTAG Technologies SCIP modules overcome these obstacles.
While a full ProVision system allows development and execution of integrated JTAG/boundary-scan test and programming software applications, it is possible to use the same familiar user interface in a reduced functionality version within production and manufacturing. ‘ProVision Platform’ is available for test execution only, flash in-system programming (ISP) only, PLD ISP only, or of course any combination of these.
Each ProVision Platform licence includes the capability to import ProVision development archives, execute applications and review test results in the familiar TTR (Truth Table Report) format and, optionally BSD (diagnotics) or Visualizer (graphical viewer). The system also includes the built-in boundary-scan test sequencer, our acclaimed AEX (Application EXecutive) manager, for application sequencing which itself includes if, then, else and goto structures for building more complex test and programming sequences as well as report generation and results storage by serial number.
JTAG Technologies Production Integration Packages allow users to execute the full range of JTAG board test and programming applications from a ‘third party’ environment. In addition to the test oriented front-ends such as National Instruments’ LabView and TestStand, JTAG Technologies also provides support for a range of generic compilers for Microsoft and others.
For C/C++ there is PIP/DLL, for .NET framework systems such as Visual C, Visual Basic etc. we offer PIP/.NET and for older Visual Basic compilers there’s also PIP/VB. There’s even a DOS/Win command line execution package called PIP/EXE. Each PIP package includes full capability to load and launch applications to test and program boards on our DataBlaster, Explorer or new MIOS (mixed-signal) IEEE Std. 1149.x boundary-scan controllers.
As a long-standing alliance partner with National Instruments, JTAG Technologies is able to offer a wide range of high-level integration options for the National Instruments’ control and test executive packages – TestStand, LabView and LabWindows/CVi. As part of our PIP (Production Integration Packages) family our National Instruments support options have enabled our customers to seamlessly and reliably integrate high-quality boundary-scan applications into their test and device programming systems for almost 20 years.
BSD Test Diagnostics software can be added to either developer or factory run-time systems to further improve the location of faults such as net bridges (short-circuits), open pins, open nets and even ‘twisted’ connections that can occur within cable assemblies. BSD Test diagnostics reports faults in a verbose English language statement with pin level information included and can easily interpret multiple fault conditions.
Additional capability can be added to the test diagnostics package through the use of fault dictionaries that can be created for functional logic (cluster tests). These can help pin-point faults that may occur deep within a functional logic block. Test diagostics is the ideal complement to the TTR (Truth table reporter system) that is included in our ProVision developer suite and also PIPs (Production Integration Packages). BSD Test Diagnostics is a standard feature of the Symphony family of run-time systems that have been developed to allow JTAG Technologies applications to be executed on third party ATE systems.
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