The JTAG Provision Boundary-scan Integrated Development Environment (IDE) is a test and programming application development suite that is used during product development, production and manufacturing to generate boundary-scan tests and in-system programming applications for assembled PCBs and systems. This integrated professional JTAG boundary-scan development environment (IDE) software tool is fully automated and supports the import of design data from over 30 different EDA and CAD/CAM systems. Other key data inputs are JTAG device BSDL (description) models and a large, well-maintained model library describing thousands of non-JTAG devices including memories, bus logic, and other active and passive parts.
How it works
With the ProVision boundary-scan software suite you can rapidly generate a wide range of test and programming applications using a project database built up from the inputs above. All applications can be optimized, validated and run within the ProVision environment prior to delivery of the finished test sequences to the manufacturing and/or testing facility. ProVision comes with a built-in boundary-scan test sequencer for production ready test plans
ProVision’s development features are tightly integrated with JTAG Technologies’ advanced test coverage analysis tool and also with JTAG Visualizer graphical display system for design schematics and layouts. You can use these professional JTAG tools to quickly assess the thoroughness of the test during development and to make improvements prior to release.
JTAG Functional Test system (JFT) is a simple to use DLL Application Program Interface (API) with a series of software modules that support boundary-scan test (testing single pin nets) and programming activities under Python, National Instruments’ LabVIEW and Microsoft .NET framework. Using JFT users can create JTAG/boundary-scan test application scripts, LabVIEW (Boundary-scan VI’s). .Net or programs for PCB assemblies and systems that control individual driver/sensor pins, groups of pins declared as variables or register bits.
These applications are typically used to test logic devices or mixed signal clusters and can also be transformed into re-usable test ‘modules’. Pairing JFT with JTAG CoreCommander emulative test modules gives an effective, low-cost system for performing tests through embedded device peripherals (ADCs, Memory Controllers etc..)
JTAG Visualizer is an advanced graphical and layout viewer and data management system for PCB schematics and layouts. Visualizer integrates seamlessly with the JTAG Technologies family of boundary-scan products such as the ProVision application development platform. It accepts PCB data from a variety of CAD, CAM and EDA tools. In design, Visualizer provides DfT (design for test) feedback to the user by enabling a graphical view of fault coverage on their design. In manufacture and test, Visualizer can be used to highlight faulty nets (short circuits, opens, stuck-ats etc.) in both layout and schematics views. Visualizer also supports cross-probing between schematics and layout as well as a layout underside ‘flip’ view mode.
Building high speed memory cluster and connectivity tests with CTPG_M and a supporting CoreCommander module that allows communication with your device’s internal IP is all that is needed to build high-speed memory and connectivity cluster tests in ProVision.
Led by an increasing desire to test DDRx and other memory types at true system speed JTAG Technologies has developed the new CoreCommander Test Program Generator (CTPG_M) for ProVision. CTPG_M overcomes many of the issues associated with testing of memory clusters using conventional boundary-scan (IEEE Std 1149.1) techniques, including the lack of a boundary-scan register (generally in smaller CPUs), insufficient access to all memory signals (most notably synchronous memory clocks) and also the inability to test using write/read cycles running at full system speed. By using the power of the embedded emulation/debug logic and the embedded memory controller, tests can be developed automatically to overcome the issues listed above, allowing faster and more effective testing. The system utilises existing debug/emulation support options built-into microprocessors or downloaded into FPGAs (see CoreCommander). CTPG_M is available now as an option to JTAG ProVision software (CD 23 and above). It is fully compatible with all JTAG Technologies tester hardware and diagnostics system allowing pin-level diagnostic reports to be produced for test engineers, production technicians and others. Test results can thus also be viewed in layout or schematic views provided by JTAG Technologies Visualizer tools.
JTAG Technologies’ ‘Classic’ Production Stand-Alone package (PSA) has, for many years, been the standard execution system operated in CEM and OEM factories when an independent boundary-scan test and/or device programming station is required. Introduced in the late 1990s to support applications generated by our ‘Classic’ development tools, several thousand PSA systems are still in use today. For new projects however ProVision Platform run-time system is usually recommended
Using PSA, test engineers can build sequences of applications in the built-in AEX (Application EXecutive) manager using if, then, else, and goto capabilities. Sequence builders can also include additional capabilities through DOS/Win command line calls, create serial number logged test reports, export tests results to a database etc.. PSA includes drivers for all JTAG Technologies controller hardware past and present.
While a full ProVision system allows development and execution of integrated JTAG/boundary-scan test and programming software applications, it is possible to use the same familiar user interface in a reduced functionality version within production and manufacturing. ‘ProVision Platform’ is available for test execution only, flash in-system programming (ISP) only, PLD ISP only, or of course any combination of these.
Each ProVision Platform licence includes the capability to import ProVision development archives, execute applications and review test results in the familiar TTR (Truth Table Report) format and, optionally BSD (diagnotics) or Visualizer (graphical viewer). The system also includes the built-in boundary-scan test sequencer, our acclaimed AEX (Application EXecutive) manager, for application sequencing which itself includes if, then, else and goto structures for building more complex test and programming sequences as well as report generation and results storage by serial number.
CoreCommander can be used as interactive jtag hardware debug tool via its high-level GUI. In this jtag interface register access commands or full memory reads and writes can be selected and executed with a direct view of the results. Sequences of commands can be re-played within the interactive window or exported into a Python editor. The interactive usage is particularly valuable during hardware bring up and debugging in design and (field) service
While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote ‘kernel-centric’ testing. Similarly, in the case of today’s Field Programmable Gate Arrays (FPGAs) test engineers can ‘bridge’ from the JTAG interface to the resources of the gate array itself. Our CoreCommander FPGA product implements a ‘translator’ interface that allows our JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone, CoreConnect, AXI, Avalon etc.).
CoreCommander is also available through our webshop.
JTAG Technologies Production Integration Packages allow users to execute the full range of JTAG board test and programming applications from a ‘third party’ environment. In addition to the test oriented front-ends such as National Instruments’ LabView and TestStand, JTAG Technologies also provides support for a range of generic compilers for Microsoft and others.
For C/C++ there is PIP/DLL, for .NET framework systems such as Visual C, Visual Basic etc. we offer PIP/.NET and for older Visual Basic compilers there’s also PIP/VB. There’s even a DOS/Win command line execution package called PIP/EXE. Each PIP package includes full capability to load and launch applications to test and program boards on our DataBlaster, Explorer or new MIOS (mixed-signal) IEEE Std. 1149.x boundary-scan controllers.
As a long-standing alliance partner with National Instruments, JTAG Technologies is able to offer a wide range of high-level integration options for the National Instruments’ control and test executive packages – TestStand, LabView and LabWindows/CVi. As part of our PIP (Production Integration Packages) family our National Instruments support options have enabled our customers to seamlessly and reliably integrate high-quality boundary-scan applications into their test and device programming systems for almost 20 years.
BSD Test Diagnostics software can be added to either developer or factory run-time systems to further improve the location of faults such as net bridges (short-circuits), open pins, open nets and even ‘twisted’ connections that can occur within cable assemblies. BSD Test diagnostics reports faults in a verbose English language statement with pin level information included and can easily interpret multiple fault conditions.
Additional capability can be added to the test diagnostics package through the use of fault dictionaries that can be created for functional logic (cluster tests). These can help pin-point faults that may occur deep within a functional logic block. Test diagostics is the ideal complement to the TTR (Truth table reporter system) that is included in our ProVision developer suite and also PIPs (Production Integration Packages). BSD Test Diagnostics is a standard feature of the Symphony family of run-time systems that have been developed to allow JTAG Technologies applications to be executed on third party ATE systems.
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