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SCIL (Scan Configured Interface Logic) modules are a range of hardware functions usually pre-programmed into pods that take the place of a regular TAP pod within the JT 37×7 DataBlaster’s QuadPod system. Alternative ‘hosts’ for SCIL functions can also be the JT 2111/MPV (desktop DIOS) or the JT 5112 (MIOS). Currently available SCIL modules for enhancing test coverage are counter/timer and pattern generator/comparator units. Other SCIL modules are used in tandem with a SCIP (Serial Controlled In-system Programming) software options for in-system programming purposes. SCIP/SCIL combinations are used for programming Freescale parts via BDM, and Mono8 interfaces. SPI, I2C, SWD, and Microchip custom one-wire protocols are also supported.
Further SCIL module functions can be developed upon request, simply contact us or your local sales office.
JTAG Technologies BSDL generation/verification system combines advanced software with a unique hardware interface and automatically verifies an existing BSDL (Boundary-Scan Description Language) file or creates a BSDL file for the device if none exists from a known good sample device. The system complies with the recognized standard for BSDL descriptions – IEEE Std. 1149.1b . BSDL files describe the boundary-scan characteristics of a specific device in terms of scan register lengths, ID codes, instruction codes, etc.. and are a fundamental input to ATPG (e.g. ProVision) and other boundary-scan software tools.
JTAG TapCommunicator facilitates remote execution and diagnostics of boundary-scan applications, regardless of distance or environmental difficulties. The off-the-shelf system is based on a one gigabit ethernet connection (IEEE Std 802.3z) providing virtually unlimited range between the controller and target. TapCommunicator is based on the ‘licencable’ TapSpacer IP, technology that allows any (packetised) communication link to be used. For solutions using communication links other than Ethernet, contact JTAG Technologies.
The standard TapCommunicator system consists of an “uplink” or primary module (JT 2143), located in proximity to the boundary-scan controller, and one or more “downlink” or secondary (JT 2144) modules at the target. Licenced TapSpacer systems will work in a similar way though it is expected the compact logic code (for uplink and downlink) will be integrated into the users own ASIC or FPGA.
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