Reducing the PCB Bone Pile: Optimizing Test Strategy
We are often not aware, how to reduce the PCB bone pile. The answer is : optimizing the test strategy. Having worked within an established company in the world of PCB assembly testing for many years we still come across companies (OEMs) who will tell us, “We don’t need to test, because we demand that the contract manufacturer (CM) only send us 100 percent working boards.” But, demanding and receiving are two different matters. No one can totally accomplish this, and even if they could, what does it actually cost? There’s an old saying in the engineering industry: “If it hasn’t been tested, then it doesn’t work” — rather, you should assume it doesn’t work. Most people however assume the opposite, and that is where the problems start. So the question remains how to optimze your test strategy.
ELECTRONICS WEEKLY – SEPTEMBER 2019 – JTAG EVOLUTION
Confusion about what is or isn’t JTAG is a continuing debate. The acronym stands for the Joint Test Action Group, the committee of engineers who defined the boundary-scan standard (IEEE std 1149.1) between 1986 and 1990.
As JTAG Test tools evolve to match use cases this article describes what is and what isn’t JTAG?
We like to keep you informed
The many faces of the JTAG interface port
For many the term “JTAG” is still a point of confusion; for some engineers it is a device-programming port while for others it is for plugging in a microprocessor emulator or debugger, whereas, in fact, it was originally devised for neither. JTAG is an acronym of “Joint Test Action Group”, and initially the aim was to provide an alternative system to aid circuit board assembly testing, i.e. for detecting and diagnosing assembly errors such as solder shorts, lifted pins and missing/badly-placed components. The Group in JTAG refers to a small number of test professionals who met over a period of four to five years from 1985, to devise a scheme to embed test circuitry into digital devices with the aim of assisting in the structural test of PCBA(s). Similar schemes had been developed unilaterally by device manufacturers, such as IBM’s LSSD, but at that point there was no interoperability standard that all vendors could comply to. By 1990, the JTAG system, also known as “boundary-scan”, was officially an IEEE standard number 1149.1.
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Interconnect testing with boundary scan
Interconnect testing with boundary-scan is a critical part of ensuring the reliability and functionality of complex electronic systems. Here’s how it works:
- Boundary Scan Architecture: Boundary scan testing relies on a specialized hardware infrastructure embedded in digital devices. Each device in the chain, such as microcontrollers, FPGAs, or other digital ICs, includes a boundary scan register (BSR) that provides access to its input and output pins. These registers form a daisy-chain network that connects all the devices on the board or in a system.
- Scan Chains: The boundary scan registers are connected in a series or daisy-chain fashion, creating a “scan chain” that spans all the devices on the PCB. This allows for serial data shifting through all the devices, providing access to their inputs and outputs.
- Test Access Port (TAP): A Test Access Port (TAP) controller, often implemented using a dedicated chip, is used to control the scanning process. It communicates with each boundary scan register and manages the serial data shifting. The TAP controller typically conforms to the IEEE 1149.1 JTAG standard.
- Interconnect Testing:
- Open and Short Detection: Boundary scan can detect open and short-circuit faults in interconnections between devices. By applying test patterns and monitoring responses, it’s possible to identify faulty connections.
- Cross-Talk and Impedance Testing: Advanced boundary scan techniques can also evaluate signal integrity by assessing cross-talk and impedance mismatches between signal lines.
- Functional Testing: While boundary scan primarily focuses on interconnect testing, it can also be integrated with functional testing. This means you can execute functional tests on the digital devices in your system while utilizing the boundary scan infrastructure for interconnect testing.
- Debugging and Diagnosis: Boundary scan is a valuable tool for debugging PCBs and identifying the location of faults. When a fault is detected, it can be traced back to the specific device and interconnect, making it easier to pinpoint the issue for repair or redesign.
- Automated Testing: Boundary scan testing can be automated, making it suitable for high-volume production testing. Automated test scripts can be created to perform various interconnect and functional tests, streamlining the manufacturing process.
- Benefits: The primary benefits of interconnect testing with boundary scan include increased fault coverage, reduced testing costs, faster fault diagnosis, and the ability to perform tests on devices that might otherwise be challenging to access physically.
In summary, interconnect testing with boundary scan is a powerful method for ensuring the integrity of interconnections on PCBs and digital devices. It is a valuable tool for manufacturing and debugging, particularly in complex electronic systems where traditional testing methods may be insufficient.