Reducing the PCB Bone Pile: Optimizing Test Strategy
We are often not aware, how to reduce the PCB bone pile. The answer is : optimizing the test strategy. Having worked within an established company in the world of PCB assembly testing for many years we still come across companies (OEMs) who will tell us, “We don’t need to test, because we demand that the contract manufacturer (CM) only send us 100 percent working boards.” But, demanding and receiving are two different matters. No one can totally accomplish this, and even if they could, what does it actually cost? There’s an old saying in the engineering industry: “If it hasn’t been tested, then it doesn’t work” — rather, you should assume it doesn’t work. Most people however assume the opposite, and that is where the problems start. So the question remains how to optimze your test strategy.
The many faces of the JTAG interface port
For many the term “JTAG” is still a point of confusion; for some engineers it is a device-programming port while for others it is for plugging in a microprocessor emulator or debugger, whereas, in fact, it was originally devised for neither. JTAG is an acronym of “Joint Test Action Group”, and initially the aim was to provide an alternative system to aid circuit board assembly testing, i.e. for detecting and diagnosing assembly errors such as solder shorts, lifted pins and missing/badly-placed components. The Group in JTAG refers to a small number of test professionals who met over a period of four to five years from 1985, to devise a scheme to embed test circuitry into digital devices with the aim of assisting in the structural test of PCBA(s). Similar schemes had been developed unilaterally by device manufacturers, such as IBM’s LSSD, but at that point there was no interoperability standard that all vendors could comply to. By 1990, the JTAG system, also known as “boundary-scan”, was officially an IEEE standard number 1149.1.
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Faster repair – Testing of electronics in the era of miniaturization
The test plan for a product should cover the whole product life-cycle and include: prototype debugging, manufacturing tests and field service repairs. The tools that can be used to locate a problem on a failing Printed Circuit Board Assembly (PCBA) depend on whether design data of the board is available or not, and whether test programs for the board already exist.
JFT – Functional electronics testing without a single line of code (by Etteplan)
Testing of an embedded digital system, a combination of electronics and software, has traditionally required some sort of embedded software specifically created for testing. These test versions are downloaded to the product’s processor before testing is possible. ”A significant amount of work and project time is often spent on producing test versions of the embedded software and possibly FPGA code”, tells Senior Project Manager Ilpo Harjumäki.
”A new testing technology we have started to employ makes these separate test versions redundant. This new technology has been utilized within Etteplan for almost two years now” tells Ilpo Harjumäki proudly. The new solution is based on a combination of JTAG Functional Testing – JFT, and National Instrumenst ‘LabVIEW’.
Based on JTAG
The JTAG/boundary scan pcb assembly test method is well-established. It is a separate function within the key ICs used in an assembley. When in use, the relevant states (of device pins) are clocked to the outputs of the chained circuits using a serial bus. The input states are then read respectively and compared. However using the latest, essentially more flexible JFT system from JTAG Technologies a single pin or group of pins can be driven into a certain state to be read. With the addition of CoreCommander routines users can also leverage the power of a microprocessor core to a desired value into the processor’s registers, setting up internal peripherals such as ADCs, DACs, PHYs and UARTS.
”It’s as if this technology was made for us since Etteplan’s Procket testers support LabVIEW software”, praises Ilpo Harjumäki.
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