JTAG Technologies is committed to helping you succeed with boundary-scan. We will ensure that your organisation gets the maximum return on investments and receives the greatest benefits from this technology. Look through our support section for whatever kind of information you might need and feel free to contact us if the answer to your question is not provided. For registered users, this section provides access to additional information and downloads.

NEWS & PUBLICATIONS

Visualizer with Features for Faster Debug

JTAG Technologies provides high integrity interface to MAC-Panel SCOUT

Map your JTAG Test Access with Altium Designer

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FAQs

There is no limit to the chain architecture that ProVision can handle. Fanout considerations and chain cycle speed would enter into the decision as to how long a chain to implement. Refer to the DFT booklets for more information. ProVision constructs your chain topology for you, automatically, so you don’t need to input it and can be certain it’s error-free.

There is no limit to the number of chains that the JTAG Technologies software can handle, and there is no loss in test coverage if you decide to have multiple chains. In many cases, partitioning your board into more than one chain will give you greater design flexibility and may improve the performance of your boundary-scan operations. Therefore, we strongly recommend that you consider using more than one chain on your board. For more detail, refer to our DFT booklets, one for board-level design and the other for system-level design.

Read the BSDL file published by the IC manufacturer. If it is compliant, it should say so in the notes. Also check the BSDL for special compliance requirements. In some cases it may be necessary to hold specified pins at defined voltage levels for the part to perform boundary-scan operations. If in doubt, please contact JTAG Technologies for advice.

In many cases, only a fraction of the ICs on a board need to contain boundary-scan in order to test a significant number of nets. Many boundary-scan devices tend to be complex ICs (FPGAs, PLDs, microprocessors, ASICs, etc.) with a large number of I/Os and therefore are capable of providing direct access to a large number of nets. Also, through the use of DIOS modules, you can greatly increase the test coverage. JTAG ProVision’s fault coverage feature will tell you the attainable testability and your actual coverage.

Very little. Boundary-scan helps eliminate or reduce the number of test points required on a board and may result in a net saving of real estate and a simpler layout. The space required to add a small number of passive devices for TAP lead termination and the TAP header is often offset by the test point reduction. Refer to the JTAG Technologies design guidelines for specifics.

DOWNLOADS & WHITEPAPERS

When does boundary-scan make sense?

Support Services

JTAG Technologies overview

Happy to serve you!

We have been able to solve thousands of board test problems by actively engaging with our customers. Once you become a JTAG Technologies customer you are an integral part of our business with free access to our world-wide support network.

VIDEOS

Advantages and applications of boundary-san

JTAG Technologies, the future for your ATE

An Introduction to JTAG Maps

Events

APEX 2019, San Diego

Location:  Convention Center, San Diego – Stand number:  2914

  • 29/01/2019 - 31/01/2019
  • All Day

Webinars

Introduction to boundary-scan

An eye-opener in the world of structural testing using JTAG/boundary-scan aka IEEE Std 1149.1.
Many electronics assemblies already include JTAG/boundary-scan test circuitry which is either underused or not used at all. This webinar aims to inform test and development engineers of the possibilities of this built-in test and device programming feature.
Includes sections on –
* Device-level technology
* EXTEST and other instructions
* Board-level test and programming possibilities
* Options for test generation
* Hardware controller options
* JTAG for emulation testing

  • 17/01/2019
  • CET
  • 10:30 am

JTAG Testing (and more) using Core Emulation

JTAG testing is synonymous with boundary-scan (IEEE Std 1149.1). However not all devices with a JTAG port support boundary-scan and some that do have restricted access to some signal pins, and what about access to analog functions such as built- in ADC and DAC in today’s mjcros? This webinar discusses how JTAG Technologies CoreCommander functions can be used to exploit the micro’s core (e.g. ARM, TriCore, MIPs…) power for board-level testing and more..

 

  • 23/01/2019
  • CET
  • 10:30 am

I2C and SPI – Board-level serial bus access using JTAG/Boundary-scan

I2C and its close relation SPI are used extensively in today’s electronics designs for intra-device
comms at board level. Using JTAG Technologies high-level libraries (in Python) makes it easy to
communicate these parts and generate functional test and programming applications. This webinar explains more!

 

  • 05/02/2019
  • CET
  • 10:30 am

Training

Training

JTAG Technologies offers an array of prepared and bespoke training options for designers, test engineers or production technicians. While courses are generally run at the customer's premises, JTAG Technologies can…

Consulting, experience and expertise

We have been able to solve thousands of board test problems by actively engaging with our customers. Once you become a JTAG Technologies customer you are an integral part of our business with free access to our world-wide support network.