JTAG Technologies is committed to helping you succeed with boundary-scan. We will ensure that your organisation gets the maximum return on investments and receives the greatest benefits from this technology. Look through our support section for whatever kind of information you might need and feel free to contact us if the answer to your question is not provided. For registered users, this section provides access to additional information and downloads.


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There is no limit to the chain architecture that ProVision can handle. Fanout considerations and chain cycle speed would enter into the decision as to how long a chain to implement. Refer to the DFT booklets for more information. ProVision constructs your chain topology for you, automatically, so you don’t need to input it and can be certain it’s error-free.

There is no limit to the number of chains that the JTAG Technologies software can handle, and there is no loss in test coverage if you decide to have multiple chains. In many cases, partitioning your board into more than one chain will give you greater design flexibility and may improve the performance of your boundary-scan operations. Therefore, we strongly recommend that you consider using more than one chain on your board. For more detail, refer to our DFT booklets, one for board-level design and the other for system-level design.

Read the BSDL file published by the IC manufacturer. If it is compliant, it should say so in the notes. Also check the BSDL for special compliance requirements. In some cases it may be necessary to hold specified pins at defined voltage levels for the part to perform boundary-scan operations. If in doubt, please contact JTAG Technologies for advice.

In many cases, only a fraction of the ICs on a board need to contain boundary-scan in order to test a significant number of nets. Many boundary-scan devices tend to be complex ICs (FPGAs, PLDs, microprocessors, ASICs, etc.) with a large number of I/Os and therefore are capable of providing direct access to a large number of nets. Also, through the use of DIOS modules, you can greatly increase the test coverage. JTAG ProVision’s fault coverage feature will tell you the attainable testability and your actual coverage.

Very little. Boundary-scan helps eliminate or reduce the number of test points required on a board and may result in a net saving of real estate and a simpler layout. The space required to add a small number of passive devices for TAP lead termination and the TAP header is often offset by the test point reduction. Refer to the JTAG Technologies design guidelines for specifics.


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Introduction to boundary-scan

An eye-opener in the world of structural testing using JTAG/boundary-scan aka IEEE Std 1149.1. Many electronics assemblies already include JTAG/boundary-scan test circuitry which is either underused or not used at all.

This webinar aims to inform test and development engineers of the possibilities of this built-in test and device programming feature.

Includes sections on:

*Device-level technology * EXTEST and other instructions * Board-level test and programming possibilities * Options for test generation * Hardware controller options


  • 20/01/2021
  • EU / CEST
  • 10:30 am

Boundary-scan Testing of PCBAs – Automated Generation Tools

Follow-up session to ‘An introduction to boundary-scan’. Featuring:

* Options for JTAG application development (ATPG vs Scripting)

* What can be done ‘automatically’

* Analysing the Results

This webinar covers how effective boundary-scan board (PCBA) tests can be generated without cryptic coding. JTAG Technologies fill-in-the-blanks approach is shown and the different test types created are explained.

  • 10/02/2021
  • EU / CEST
  • 10:30 am

Assessing PCBA ‘testability’ and JTAG ‘accessibility’ from schematic data

An introduction to JTAG/Boundary-scan fault coverage analysisFeaturing:

* Free and low-cost tools for exposing accessibility

* Advanced tools for precise net-level analysis

* Presentation of fault coverage results

Fault coverage analysis is an important step in the design-for-test (DFT)process which is also an integral part of of the design teams workload. Early feedback of coverage issues at the schematic entry stage can avoid costly re-spins at later stages which lengthen time-to market which in turn can massively reduce profitability over a product’s life.

  • 10/03/2021
  • EU / CEST
  • 10:30 am


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Consulting, experience and expertise

We have been able to solve thousands of board test problems by actively engaging with our customers. Once you become a JTAG Technologies customer you are an integral part of our business with free access to our world-wide support network.