A JTAG interface (TAP) is a special interface added to a chip. Depending on the version of JTAG/boundary-scan, two, four, or five pins are added. The four and five pin interfaces are designed so that multiple chips on a board can have their JTAG lines daisy-chained together if specific conditions are met.
The two pin interface is designed so that multiple chips can be connected in a star topology. In either case a test probe need only connect to a single “JTAG port” (TAP or test access port) to have access to all chips on a circuit board.
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