A protocol for testing the interconnection of low-cost, complex memory ICs
This standard defines a protocol for testing the interconnection of low-cost, complex memory ICs where additional pins for testing are not available and implementation of boundary-scan within devices such as memory ICs is not feasible. Since memory device interconnect testing is already possible using JTAG ProVision and 1149.1, the use of IEEE 1581 may be considered an alternative approach. Also known by the acronym ‘SCIT’ (Static Component Interconnect Test protocol) the standard uses an arrangement of exclusive OR gates on the address bus inputs with feedback given via data bus outputs a ‘white paper’ with more in depth details can be found here.
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