Frequently asked questions

There is no limit to the chain architecture that ProVision can handle. Fanout considerations and chain cycle speed would enter into the decision as to how long a chain to implement. Refer to the DFT booklets for more information. ProVision constructs your chain topology for you, automatically, so you don’t need to input it and can be certain it’s error-free.

There is no limit to the number of chains that the JTAG Technologies software can handle, and there is no loss in test coverage if you decide to have multiple chains. In many cases, partitioning your board into more than one chain will give you greater design flexibility and may improve the performance of your boundary-scan operations. Therefore, we strongly recommend that you consider using more than one chain on your board. For more detail, refer to our DFT booklets, one for board-level design and the other for system-level design.

Read the BSDL file published by the IC manufacturer. If it is compliant, it should say so in the notes. Also check the BSDL for special compliance requirements. In some cases it may be necessary to hold specified pins at defined voltage levels for the part to perform boundary-scan operations. If in doubt, please contact JTAG Technologies for advice.

In many cases, only a fraction of the ICs on a board need to contain boundary-scan in order to test a significant number of nets. Many boundary-scan devices tend to be complex ICs (FPGAs, PLDs, microprocessors, ASICs, etc.) with a large number of I/Os and therefore are capable of providing direct access to a large number of nets. Also, through the use of DIOS modules, you can greatly increase the test coverage. JTAG ProVision’s fault coverage feature will tell you the attainable testability and your actual coverage.

Very little. Boundary-scan helps eliminate or reduce the number of test points required on a board and may result in a net saving of real estate and a simpler layout. The space required to add a small number of passive devices for TAP lead termination and the TAP header is often offset by the test point reduction. Refer to the JTAG Technologies design guidelines for specifics.

We offer training courses to match your needs. Learning to use the primary development tools, JTAG ProVision and JTAG Visualizer, requires one to two days, assuming familiarity with PCs and the principles of board testing. Training for use of the production tools, such as PSA, the stand-alone run-time tool, requires half a day, including the use of the diagnostic software. More about training.

All customers on maintenance receive free software updates. For example, JTAG ProVision is available free of charge to all users with valid maintenance contracts and existing licenses to the earlier development tools. In addition to receiving free updates, maintenance subscribers have access to restricted areas on our website.

Contact us for more information on software maintenance.

We have factory-trained field engineers located around the world (9 in North America alone) and are readily available via email and phone. Normally, you would have one FAE assigned to you, based on proximity. This FAE is backed-up by the entire support team. Refer to our Service page.

JTAG ProVision is fully compatible with dot6. The generators automatically detect the presence of 1149.6-compliant BSDL files and develop the necessary tests to verify all testable connections; both AC and DC coupled, single-ended and differential and any combination thereof. Furthermore, ProVision ‘s provides complete diagnostics, in English, for dot6 failures.

JTAG ProVision supports a huge variety of NOR and NAND flash devices from virtually all of the major manufacturers. The software includes a library consisting of models for thousands of devices, and we continually update the library as new devices come to market. We also support many devices with embedded flash from vendors such as Texas Instruments, ST Micro, and Freescale Semiconductor.

Virtually all commercial EDA systems produce netlists that can be imported into JTAG ProVision. If a particular netlist is not supported, please contact JTAG Technologies so support may be added.

JTAG ProVision allows you to change settings using Net Explorer. The graphical tooltip shows you instantly the details for any net or node.

There is no standard for the TAP connector. However, we recommend that you use a consistent approach in all of your designs with sufficient conductors to meet your needs. We suggest 3 different size headers (10 pins, 14, and 20) depending on your application. Refer to the DFT booklet for details.

JTAG ProVision includes a large number of models for non-scan devices when the software is shipped by JTAG Technologies. Additional models can be created using ProVision’s model editor, or by requesting a model from JTAG Technologies. Also, IBIS models (Input/Output Buffer Information Specification) can be easily imported into ProVision.

JTAG ProVision (beginning with CD10) includes the ability to import design files created with JTAG Classic. Once imported, the design can be updated and maintained in the normal manner using JTAG ProVision. The additional features of JTAG ProVision will enhance your ability to make complex changes in projects that were first developed in the Classic tools.

During board design and test development, the engineers can use Visualizer to see their progress in achieving testability of their design. The software will show them, on the schematic, which portions of the board can be tested with boundary-scan and which portions cannot. Then they can take proactive steps to correct the shortcomings, prior to even laying out the board for the first time. So Visualizer can be a big time-saver and a big money-saver by avoiding unnecessary layout cycles.

The second major use of Visualizer is in repair, after a boundary-scan test has detected a failure on a board. Visualizer helps speed the repair process, and makes a significant reduction in the quantity of paper, by showing the troubleshooter on the schematic and layout where the point of failure is.

For schematic viewing with JTAG Visualizer, we have extractors for Cadence (Orcad), Mentor (all platforms), and Zuken CR-5000. We have layout extractors for Cadence Allegro, Mentor (all platforms), Zuken CR-5000 and Cadif format, Altium P-CAD, DDE Supermax ECAD, and Intercept Pantheon. Additional extractors are planned.

You can choose to have either a hardware key (often called a dongle) to control your software license or assign your license to the MAC ID of the computer on which the software will be used. The hardware key is available as a USB or parallel port device.

Our standard software licenses are permanent. However, if you wish to use our software for a limited period of time, simply get in touch and we can always make you an offer fit for your specific situation.

All of the JTAG tests and programming applications can be run by any of our PIP (production integration) software packages. There are PIP versions for National Instruments’ LabVIEW, LabWindows, and TestStand as well as software for integration with Visual Basic and DLL C/C++-based programs.

At a minimum, you would need one of the production software packages, PSA for a stand-alone boundary-scan station, one of the Production Integration Packages, PIP for adding boundary-scan to an existing test platform, or one of the Symphony systems if you would like to integrate boundary-scan in an in-circuit tester or a flying probe system.

If you go with PSA or PIP, you would also need a boundary-scan controller. The type of controller would depend on how you would like to connect it to your test system (for example, PCI or USB would be two of your choices) and what type of boundary-scan applications you want to run. The Symphony systems include the hardware.

Either party, you or your CM, can prepare the tests using JTAG ProVision.  If you do this work, you will provide the manufacturer with the tests that you prepare. If you want the CM to do the test preparation, then you will provide your BSDLs and netlists to the CM for use with ProVision.

Field returns of our controllers have been extremely low. There are over 6,500 installed, some of them in operation for more than 20 years, and fewer than 1% have been returned for repair.

The range between the QuadPOD and the target depends on the test clock TCK rate and certain characteristics of the board under test. At a TCK of 10 MHz, the allowable distance is approximately 8 meters of flat cable. At 1 MHz, the range is 100 meters. For most applications, including running system tests inside an environmental chamber the distance is not a limiting factor. We also have range extenders if there is a need for an unusually long distance to the board under test.

We also offer a product that allows virtually unlimited distance to the target, TapCommunicator. This system uses an existing network, such as your corporate intranet, to provide secure, ultra-long distance connectivity.

The minimum requirement would be BSD, the diagnostic software. You would run BSD to analyze the fault report that had been previously generated when the board was tested. At run-time, the board can be assigned a serial number to match it with the corresponding fault report. You might also want to incorporate JTAG Visualizer at your repair station using Visualizer’s graphical display of the schematic and layout to simplify finding and correcting board problems.