Frequently Asked Questions - JTAG Visualizer
During board design and test development, the engineers can use Visualizer to see their progress in achieving testability of their design. The software will show them, on the schematic, which portions of the board can be tested with boundary-scan and which portions cannot. Then they can take proactive steps to correct the shortcomings, prior to even laying out the board for the first time. So Visualizer can be a big time-saver and a big money-saver by avoiding unnecessary layout cycles.
The second major use of Visualizer is in repair, after a boundary-scan test has detected a failure on a board. Visualizer helps speed the repair process, and makes a significant reduction in the quantity of paper, by showing the troubleshooter on the schematic and layout where the point of failure is.
For schematic viewing with JTAG Visualizer, we have extractors for Cadence (Orcad), Mentor (all platforms), and Zuken CR-5000. We have layout extractors for Cadence Allegro, Mentor (all platforms), Zuken CR-5000 and Cadif format, Altium P-CAD, DDE Supermax ECAD, and Intercept Pantheon. Additional extractors are planned.