JTAG Technologies

We are boundary scan.

Frequently Asked Questions - The technology

There is no limit to the chain architecture that ProVision can handle. Fanout considerations and chain cycle speed would enter into the decision as to how long a chain to implement. Refer to the DFT booklets for more information.  ProVision constructs your chain topology for you, automatically, so you don't need to input it and can be certain it's error-free.

There is no limit to the number of chains that the JTAG Technologies software can handle, and there is no loss in test coverage if you decide to have multiple chains.  In many cases, partitioning your board into more than one chain will give you greater design flexibility and may improve the performance of your boundary-scan operations. Therefore, we strongly recommend that you consider using more than one chain on your board. For more detail, refer to our DFT booklets, one for board-level design and the other for system-level design.

Read the BSDL file published by the IC manufacturer.  If it is compliant, it should say so in the notes.  Also check the BSDL for special compliance requirements.  In some cases it may be necessary to hold specified pins at defined voltage levels for the part to perform boundary-scan operations. If in doubt, please contact JTAG Technologies for advice.

In many cases, only a fraction of the ICs on a board need to contain boundary-scan in order to test a significant number of nets.  Many boundary-scan devices tend to be complex ICs (FPGAs, PLDs, microprocessors, ASICs, etc.) with a large number of I/Os and therefore are capable of providing direct access to a large number of nets.  Also, through the use of DIOS modules, you can greatly increase the test coverage.  JTAG ProVision's fault coverage feature will tell you the attainable testability and your actual coverage.

Very little. Boundary-scan helps eliminate or reduce the number of test points required on a board and may result in a net saving of real estate and a simpler layout. The space required to add a small number of passive devices for TAP lead termination and the TAP header is often offset by the test point reduction. Refer to the JTAG Technologies design guidelines for specifics.