Boundary-scan testing was originally devised by an independent committee known as JTAG (the Joint Test Action Group) which held a series of meetings throughout the late 1980s. The JTAG committee was formed by test professionals from Philips, BT, GEC, TI and others, whose objective was to provide an alternative mechanism to ICT (In Circuit Test) for the then new surface mount designs. The use of surface mount (SMT) parts meant that the component pins could not so easily be probed, and hence tested, by these traditional 'bed of nails' style testers. Since the formal introduction of boundary-scan in the 1990s adoption of this PCB test technique has accelerated due to a number of factors:
- Boundary-scan offers a low-cost formalized alternative test method to ICT or functional test
- Offers easy pin access to very fine pitch BGA and TSOP device packages
- Avoids the pin-count limitations of ICT machines
- Overcomes issues in advanced PCB manufacture (inaccessible nodes due to blind vias and buried tracks)
- Secondary function as defacto port to program CPLDs, FPGAs, Flash Memories and SPROM 'in-system'