Moving into the future: upcoming boundary-scan standards | JTAG Technologies

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Moving into the future: upcoming boundary-scan standards

There are several working groups of the IEEE currently pushing boundary-scan technology forward. Ultimately, the work of these groups may become official standards, available for deployment by chip, board, and system vendors. The principle efforts that are underway are:

IEEE 1149.1-2013: A superset and update of 1149.1 and fully compliant with it, this standard is intended to address recent developments in the interfaces between board level components. Among the additions are: a standardized initialization procedure for complex I/Os (e.g. multiple voltages within a single device, sleep modes etc..) prior to test, improved support and relaxed rules for differential drivers/receivers, allowance for no-connect pins in packages, additional support for linkage-ground-power pins, a 'segmentable' boundary-scan register and the inclusion of a unique Electronic Chip Identification (ECID) to help combat counterfeiting. There is also included clarification on use of TRST.

IEEE 1687: Also known as iJTAG, this is an extended internal JTAG architecture devised to access built-in device-level test instruments through a single 'dot1' level instruction GWEN (Gateway Enable). The Gateway alllows access to multiple instrument control registers each in turn selected by SIBs (Select Instrument Bits) that form part of the Gateway status register. Typical 'instruments' could include memory BIST cores for high-speed (DDRx) memories. The standard is supported by two new languages: ICL- Instrument Connectivity Language that defines the hardware/logic interface to the instruments IP and; PDL – Procedural Description Language (a close relative of TCL) that defines the patterns or vectors that are applied and sensed via the logic interfaces in order to invoke the instruments’ IP functions.  JTAG Technologies already  offers an IEEE 1687 tool contains all the necessary parsers and interpreters required to create working applications for 1687 compatible devices that are now emerging in some key industry sectors. 

IEEE P1149.8: A further superset of 1149.1 proposed by ICT (In-Circuit Test) equipment manufacturers to combine boundary-scan technology with proprietary capacitive plate sensor technology currently supplied under trade names such as TestJet(TM). Within IEEE P1149.8 a pin or small group of pins on a compatible part can be used to provide an AC stimulus (toggle) signal to a target component (e.g. connector or surface-mount mount IC). The capacitive plate is used to detect level changes that occur when a DUT (device under test) pin is open-circuit or bridged.

SJTAG: This effort is still in preliminary stage and is not yet a working group within the IEEE. The intention is to standardize methods for system-level testing. System-level functions are already well supported by JTAG ProVision and prior tools, with built-in capability for all of the commercially available bridging devices from National Semiconductor, Texas Instruments, Lattice Semiconductor, and Firecron.

JTAG Technologies will work closely with all of these efforts to maintain that state-of-the-art edge. For more information please visit the official IEEE website.

Further standards: