JTAG Technologies – a specialist in board (PCBA) test solutions - announces a novel system to increase fault coverage and speed-up testing on designs featuring µProcessors and FPGAs. Building on their Emulative Test & Programming (ETP) technology that offers access to the kernel of these devices, JTAG Technologies introduces a new automatic pattern sequence generator for testing connectivity and at-speed functionality between the device kernel and all types of memories including DDRx devices.
Known as CTPG_M the tool has been developed in-house to overcome many of the issues associated with testing of memory clusters using conventional mechanisms such as boundary-scan (IEEE Std 1149.1). These issues can include the lack of a boundary-scan register (generally in smaller CPUs), insufficient access to all memory signals (most notably synchronous memory clocks) and also the inability to test using write/read cycles running at full system speed. By harnessing the power of the embedded emulation/debug logic plus embedded memory controller, tests can be developed automatically that overcome the issues listed above allowing faster and more effective testing.
As part of JTAG Technologies broader range of ETP products CTPG_M aims to increase both fault coverage and test throughput on compatible designs. The system utilises embedded µProcessor and FPGA emulation support options that cover most of the chips based on the popular ARM cores, as well as cores from Analog Devices, Infineon, NXP (Freescale), TI, Microchip and Marvell (Xscale) and parts from Altera and Xilinx
CTPG_M is available now and will be shipped in the forthcoming release of JTAG Technologies software tools. It is fully compatible with all JTAG Technologies tester hardware and diagnostics system enabling pin-level diagnostic reports to be produced for test engineers, production technicians, service technicians et al. Test results can thus also be viewed in layout or schematic views provided by JTAG Technologies Visualizer tools.