Standardizing PLD programming: IEEE 1532 | JTAG Technologies

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Standardizing PLD programming: IEEE 1532

Programmable logic devices (PLDs and FPGAs) from most of the major IC vendors have complied with the original IEEE 1149.1 specification for many years.  Compliance meant that these devices could serve as board test resources and also that the devices themselves could be in-system programmed by a boundary-scan system.  Complexity arose because of the wide variety of programming algorithms and data formats in use among the vendors and device types, but despite this issue, IEEE 1149.1 has been a preferred method to program PLDs and FPGAs for many years.

An enhancement to 1149.1 was developed around the year 2000 to standardize the methodology for programming these types of devices.  With IEEE 1532, compliant devices, regardless of vendor, may be configured (written), read back, erased and verified, singly or concurrently.  The programming algorithm is described in the 1532 BSDL file.  JTAG Technologies programming tools contain support for 1532-compliant devices and automatically generate the applications.

Further standards: