IEEE 1149.7 also known as cJTAG (compact JTAG) or 'dot7' is the latest addition to the family and emcopasses a wide range of additional features for accessing cores within SOCs, managing power of the test circuitry, improving data throughput rates etc.. External to the device two (out of six) compliance classes of 'dot7' include a reduce pin count interface that manipulates the regular (dot1) state machine with only TCK and TMS signals to transmit/receive instructions and data. This reduced pin count implementation allows different connection topologies such as the 'star' configuration that simplifies the handling arrays of identical devices and devices with multiple cores. These can be boards with DSP 'farms' , multi-core CPU or Systems-on-Chip (SoC) with separate physical processors, stacked die configurations or multichip System-in-Package (SiP) modules. A further valuable feature of 'dot 7 is slectable device addressing - while the serial nature of IEEE 1149.1 makes it very difficult to communicate exclusively with one specific device in the scan chain, dot7 provides a means to address and access specific devices in the scan chain individually, without having to shift bits through the entire instruction register length of the full scan chain.