JTAG Technologies

We are boundary scan.

CoreCommander

While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote 'kernel-centric' testing. Similarly, in the case of today’s Field Programmable Gate Arrays (FPGAs) test engineers can 'bridge' from the JTAG interface to the resources of the gate array itself. Our CoreCommander FPGA product implements a 'translator' interface that allows our JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone, CoreConnect Avalon etc.).

  • JTAG control of 'processors, and FPGAs via core debug access or embedded logic
  • Most popular cores & FPGAs supported
  • Create 'at-speed' cluster tests and flash applications

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Benefits

Benefits

  • Overcomes deficiencies in boundary-scan registers
  • Works with devices not compliant to IEEE std 1149.x
  • Most popular processor cores & FPGAs supported (ARM PPC etc.)
  • Code compatible with Python for test scripting
  • Low-cost compared to other solutions.