BSDL Verifier | JTAG Technologies

JTAG Technologies

We are boundary scan.

BSDL Verifier

Using a sample boundary-scan IC, the JTAG Technologies BSDL generation/verification system automatically verifies the existing BSDL (Boundary-Scan Description Language) file or creates a BSDL file for the device if none exists, all in accordance with the IEEE 1149.1b Boundary-scan Standard. A BSDL file describes the boundary-scan characteristics of a specific device in terms of scan register lengths, ID codes, instruction codes, etc..

  • Supports up to 512 signal pins
  • Easy-to-use software and hardware
  • Creates a BSDL model from hardware
  • Includes a JT 3707 controller

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Benefits

Benefits

  • Create and verify Boundary-Scan Description Language (BSDL) files using the actual integrated circuit
  • Wizard guides the user through the generation / verification process
  • Graphical editor provides interactive preparation of pin list for PGA and BGA device packages (in case no BSDL file exists)
  • Table-structured editor generates pin list definition interactively for other device package types (in case no BSDL file exists)
  • Extensive reporting features: cell list, pin list, input list, output list, register information
  • Support for wide range of package types: PGA, BGA, QFP, TSOP, etc. with automatic wiring/netlist generation software