Boundary-scan Technology, board design for test (testability) guidelines (DFT) for PCB testing and In-System Configuration

Design-For-test (DfT) guidelines and analysis tools assist the design engineer in creating testable designs without costing extra design time. Throughout the electronics industry, manufacturers are turning to the latest device packaging technologies, such as ball grid arrays (BGAs), chip-scale packages, and other small outlines, to provide the functionality and miniaturization their customers demand.

However, the new packages are increasing the difficulty of accessing printed circuit boards for In-Circuit Testing (ICT) and in-system device configuration. These difficult access problems have been addressed by the industry through adoption of the IEEE 1149.1 boundary-scan standard (aka JTAG), allowing pin-level access – independent of the device packaging technology – to even the most crowded printed circuit board assemblies.

Nowadays almost all popular complex ICs support IEEE 1149.1 test features. At the printed circuit board level it is the responsibility of the hardware designers and project managers to use the available device IEEE 1149.1 features for achieving a better board level testability. The guidelines described in this booklet help the designer to implement board level Design For Test (DFT).