JTAG Maps for Altium
JTAG Maps is an extension to Altium Designer EDA system that allows the user/engineer to quickly assess the capabilities of the JTAG devices on their design. Until now engineers could often spend hours highlighting the boundary-scan nets of a design manually to determine fault coverage. Today the free JTAG Maps for Altium application does all this and more, freeing-up valuable time, allowing a more thorough DfT and speeding time to market.
With or without boundary-scan models – boundary-scan device models (BSDLs) are pivotal to any JTAG/boundary-scan process as they indicate precisely which pins can be controlled or observed by JTAG/boundary-scan. However JTAG Maps for Altium can work with or without BSDL models and includes an ‘assume scan covered’ option. This feature can also be used to indicate fault coverage to a connector (set to assume scan covered) or to highlight the differences in fault coverage between two equivalent parts. JTAG Maps for Altium will also automatically trace the TAPs (Test Access Ports) from schematic data. The JTAG control nets associated with the TAPs will be highlighted separately from the ‘testable’ nets.
Import as well as export – while most users will want to simply use the coverage report that JTAG Maps for Altium can provide, it is possible to import a more accurate picture. After exporting a JTAG ProVision project, the data can be sent for further analysis. A simple text-based message file containing full fault-coverage information can then be read back into JTAG Maps for display/highlighting.
Optional Developer Tools– for engineers wishing to apply JTAG/Boundary-scan tests directly onto their design JTAG Technologies can offer two further options, JTAG Live for low cost functional testing with boundary-scan and JTAG ProVision a full-blown automated test program generation and device programming system
- Rapid display of boundary-scan acessibility
- Aids DfT process
- Speeds product development
- Faster time-to-market
JTAG Maps is the ideal companion tool to Altium Designer for engineers with a responsibility for DfT (Design for Test). JTAG/Boundary-scan is widely acknowledged as the principal method for testing PCB assemblies with a digital content (utilising devices such as FPGAs, CPLDs, Microprocessors, Microcontrollers etc.). JTAG Maps allows a quick and easy view of your design’s boundary-scan test potential.
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