The JTAG/boundary-scan interface and technology is found in most of today’s electronics. The technology was standardized in 1990. Since then more standards have been added each building upon and enhancing the original standard to extend the test coverage.
Introduction
What is JTAG
JTAG/boundary-scan (IEEE Std 1149.1) is an electronic four port serial JTAG interface that allows access to the special embedded logic on a great many of today’s ICs (chips) . The JTAG accessible logic interface serves a number of functions that can include any or all of the following:
- Test logic that enables testing of connections between devices without external probes;
- Programming logic in Flash memories, CPLD’s and FPGA’s for on-board programming of these devices;
- Debug logic in microprocessors and microcontrollers used for software debugging, or to test connections with peripheral devices at speed without embedded software, or to program the embedded flash in a microcontroller.
Devices with a JTAG/boundary-scan interface and logic, are present on many of today’s Printed Circuit Board Assemblies (PCBA’s). The devices are often connected in serial (daisy chain) formation, to form a so-called ‘scan chain’ on the PCBA. An external JTAG/boundary-scan controller is used to activate the logic and complete the testing of the board and programming of devices. Using the JTAG/boundary-scan logic minimizes the amount and complexity of equipment for testing boards and for device programming in design, manufacturing and service as it removes the need for external probing and complex fixtures. Read more in our white paper.
In summary JTAG/boundary-scan saves time and costs for your board test and programming systems and more important of course also on a corporate level.
Why JTAG
JTAG boundary-scan helps your process in three ways: it saves your organization time, it is cost-effective and it strengthens the quality of your products. To explain how we do that, let’s look into some of the details.
The JTAG boundary-scan standard was developed to solve a fundamental, technical problem facing traditional PCB assembly test equipment, i.e. probing device pins in fine-pitch, high pin count SMD packages (in particular BGA’s). Embedding JTAG/boundary-scan logic in chips makes the pins readily accessible and allows test signals to be transmitted between devices, independent of the type of package or device complexity without external probing.
Testing is essential to guarantee the quality of your products. One possibility is to perform a functional test. However, functional testing has two main disadvantages: you don’t know if you covered all possible assembly defects, and íf you find a failure it is hard (time-consuming, costly) to diagnose its cause. These two shortcomings are addressed by structural testing.
But structural testing requires probing of device pins. With miniaturization, probing is no longer possible, and thus structural testing using external probes becomes impossible. With boundary-scan such external probing is no longer needed. Thus boundary-scan was developed in a way that in case of miniaturization structural testing is still possible.
In short: boundary-scan was developed to facilitate structural testing, also in case of miniaturization.
While the original standard focused on board testing, the JTAG interface was soon also used for in-system programming of devices (Flash memories, FPGAs, CPLDs, and microcontrollers). The JTAG boundary-scan standard now provides many advantages over traditional systems. Read more in the white paper “When does Boundary-scan make sense“
JTAG Testing
Traditional test equipment using probing techniques to access pins and signals on Printed Circuit Board Assemblies (PCBA’s) faces increasing challenges. First the increasing use of Surface Mount Devices (SMD), and in particular Ball Grid Array (BGA) packages, makes external probing of device pins and nets more and more complicated. Secondly the ongoing integration of functionality in a single chip, resulting in System-on-Chip (SoC) devices, results in an increase of the complexity of such devices making external control increasingly challenging. As a result the possible test coverage and the diagnostic resolution of traditional test methods decreases for boards using these technologies. When an increasing part of a PCBA can be reached via JTAG testing, both the test coverage and the diagnostic resolution via JTAG increase.
If no JTAG devices are used on a board, then of course only traditional test methods can be used to test and program a board. However, if JTAG devices are used on a PCBA then their capabilities can be used for test and programming. Depending on the design of the board and the percentage of JTAG access it is possible that only JTAG-based test and programing tools are sufficient to test and program the entire board. If only a part of the board is accessible though JTAG a combination of traditional test methods and JTAG testing provides a high test coverage. More about testing in this white paper.
Device programming
The popular JTAG/boundary-scan test and programming interface was first introduced in the early 90s when the vast majority of parts were programmed ‘off board’ using either simple bench programmers or more highly automated production programmers. At this time device programming as a service was also a booming market in its own right.
With the advent of JTAG-programmable devices, focus switched to ‘In-System’, aka ‘In-Circuit’ or ‘On-board’, programming of devices (ISP). ISP offers several advantages in terms of the reduced handling of parts (leading to less likely mechanical or static damage), easier field updates, and more flexible production processes (specific code can be provided at assembly time leading to a lower inventory of pre-programmed parts).
JTAG logic in chips
Examples of built-in resources in chips accessible through the JTAG interface are the boundary-scan register and the microcontroller debug logic. A boundary-scan register gives direct access to device pins without using the device functionality (the device core). Connections between different devices can easily be accessed for testing or programming. The boundary-scan register is at the heart of boundary-scan test and programming. Microcontroller debug registers/logic gives direct access to the microprocessor busses without using the microprocessor functionality.
The microprocessor debug logic is at the heart of emulative test and programming. Both internal and external memory peripherals connected to the processor busses can easily be accessed for testing or programming without embedded software.
How does it work
JTAG/boundary-scan provides a quick and easy method for testing electronic Printed Circuit Board Assemblies or PCBAs for manufacturing faults. It is also widely used for programming ICs such as cPLDs, FPGAs and flash memories on the circuit boards in production as well as after product manufacture if software/ firmware updates are needed.
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Firmly based on IEEE standards
The serial interface and logic were originally developed by a group of test professionals from Philips, BT, GEC, TI and others known as JTAG (the Joint Test Action Group) throughout the late 1980s. The group continued as an IEEE working group to complete the final standard which then got the official name IEEE Std 1149.1, the IEEE Standard Test Access Port (JTAG interface) and Boundary-Scan Architecture. The standard was first released in 1990. Since then enhancements have been made and the latest update was done in 2013, see IEEE 1149.1-2013.
The IEEE Std 1149.1 is often referred to by other names such as JTAG, JTAG boundary-scan, or Dot1. JTAG devices are officially referred to as IEEE 1149.1 compliant devices.
The standard defines the serial (JTAG) interface, called the Test Access Port (TAP), and the test logic architecture built into chips. One specific example of test logic is defined in the standard, the so called boundary-scan register, for testing connections between devices on a PCBA.
The TAP features four (or sometimes five) signals:
- TCK (Test clock)
- TMS (Test Mode Select)
- TDI (Test Data In)
- TDO (Test Data Out)
- TRST (Test logic Reset) (optional)
To simplify the test infrastructure within a PCBA it is common to connect the devices in serial (daisy chain) formation so that TDO from the first device connects to TDI of the next (and so on) to form a so-called scan chain.
The test logic architecture comprises of one Instruction Register (IR) and multiple Data Registers (DR). By loading an opcode in the IR with an IR-scan a specific DR is selected which is then accessed with consecutive DR-scans.
When the boundary-scan register is selected as DR, this register will control the device’s pins while isolating the primary core functions of the device.
The test logic architecture from Dot1 is defined such that other data registers (DRs) can easily be added in a chip design. For example the debug logic of microprocessors and microcontrollers or the programming logic in modern CPLDs and FPGAs. These DRs are defined in additional standards building upon and enhancing the original Dot1.
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