Moving into the future: upcoming boundary-scan standards

There are several working groups of the IEEE currently pushing boundary-scan technology forward. Ultimately, the work of these groups may become official standards, available for deployment by chip, board, and system vendors. The principle efforts that are underway are:

IEEE 1149.7: A superset of 1149.1 and fully compliant with it, directed at reducing the pincount and enhancing the functionality of the link between 1149.1 test systems and targets.

IEEE P1581: This working group is defining a standard protocol for testing the interconnection of low-cost, complex memory ICs where additional pins for testing are not available and implementation of boundary-scan within the memory ICs is not feasible. Since memory device interconnect testing is already possible using JTAG ProVision and 1149.1, the work of P1581 may be thought of as an alternative approach.

SJTAG: This effort is still in preliminary stage and is not yet a working group within the IEEE. The intention is to standardize methods for system-level testing. System-level functions are already well supported by JTAG ProVision and prior tools, with built-in capability for all of the commercially available bridging devices from National Semiconductor, Texas Instruments, Lattice Semiconductor, and Firecron.

JTAG Technologies will work closely with all of these efforts to maintain that state-of-the-art edge. For more information please visit the official IEEE website.