Koos den Hollander, Test Design Engineer, Siemens VDO 
For Siemens VDO, conventional test methods were out of the question. Moreover, diagnosis alone could take days, and optical and other conventional methods could not reach the pins. Yet, with higher production volumes for direct sale to end-users the time left for testing is only about 35 seconds for each board.

The solution? VDO uses a single JTAG Technologies’ boundary-scan component (the ASIC) which gives access to most of the nets of the board for testing and on-board rogramming. 
 
“Real high-volume consumer applications will even balk at adding four extra pins to an IC, but they pay for this by having to add test points. The more components, the more test points, and at a certain moment this itself causes problems. Last-minute changes, for example, mean that you have to set up the bed of nails again. If you have a large production line waiting, changing the bed of nails is not so easy. Boundary-scan eliminates the need for many of these test points, which also gives you more board space and more design freedom and a better failure localization. With careful design, even a single boundary-scan IC gives you most of the technique’s benefits. It allows us to make hardware much earlier, for example, well before we develop the final test software."
 
"With our third generation product we were able to generate the boundary-scan vectors in parallel with the product development itself. Boundary-scan also gives much better fault diagnosis, because you know not only the fault but also the location - including faults in clusters. For us, the other major benefit has been the in-system programming. Before, there were very different programming steps taking too much time and operator involvement, and causing many scrap units. The package pins are so small and fragile that the action of simply putting them in the programmer was a risky one. Bent IC pins are particularly annoying because all the signals can seem to be fine, and the faults aren’t always easy to spot.
 
The four flash memories were a particular problem. “With our previous equipment, we had to program the flashes before placement, solder them and then use test software to check whether they worked, which is pretty trivial because the test software will never run if something is wrong with the memories. Moreover, if the test software does not run, you are in deep trouble because up to 100 signals can be at fault. We also had faults like our thinking that a device was programmed, only to find later that it wasn’t. Now, we just assemble blank memories: we buy them and then mount them – end of story. Within the 35 seconds available to us, we can test the complete main board and program 16 Mbytes of flash memory using Boundary-scan.”